at91sam9263.h

Centrality Atlas II development software

#define AT91SAM9263_USART_IF                    0x04c

  /* Serial Synchronous Controller (SCC) */
#define AT91SAM9263_SSC_SIZE                    0x50
#define AT91SAM9263_SSC_CR                      0x00
#define AT91SAM9263_SSC_CMR                     0x00
#define AT91SAM9263_SSC_RCMR                    0x04
#define AT91SAM9263_SSC_RFMR                    0x10
#define AT91SAM9263_SSC_TCMR                    0x14
#define AT91SAM9263_SSC_TFMR                    0x18
#define AT91SAM9263_SSC_RHR                     0x1c
#define AT91SAM9263_SSC_THR                     0x20
#define AT91SAM9263_SSC_RSHR                    0x24
#define AT91SAM9263_SSC_TSHR                    0x
#define AT91SAM9263_SSC_RCxR(x)                 (0x38 + 4*x)
#define AT91SAM9263_SSC_RC0R                    0x38
#define AT91SAM9263_SSC_RC1R                    0x3c
#define AT91SAM9263_SSC_SR                      0x40
#define AT91SAM9263_SSC_IER                     0x44
#define AT91SAM9263_SSC_IDR                     0x48
#define AT91SAM9263_SSC_IMR                     0x4c

  /* AC'97 Controller (AC97C) */
#define AT91SAM9263_AC97C_SIZE                  0x60
#define AT91SAM9263_AC97C_MR                    0x08
#define AT91SAM9263_AC97C_ICA                   0x10
#define AT91SAM9263_AC97C_OCA                   0x14
#define AT91SAM9263_AC97C_CARHR                 0x20
#define AT91SAM9263_AC97C_CATHR                 0x24
#define AT91SAM9263_AC97C_CASR                  0x28
#define AT91SAM9263_AC97C_CAMR                  0x2c
#define AT91SAM9263_AC97C_CBRHR                 0x30
#define AT91SAM9263_AC97C_CBTHR                 0x34
#define AT91SAM9263_AC97C_CBSR                  0x38
#define AT91SAM9263_AC97C_CBMR                  0x3c
#define AT91SAM9263_AC97C_CORHR                 0x40
#define AT91SAM9263_AC97C_COTHR                 0x44
#define AT91SAM9263_AC97C_COSR                  0x48
#define AT91SAM9263_AC97C_COMR                  0x4c
#define AT91SAM9263_AC97C_SR                    0x50
#define AT91SAM9263_AC97C_IER                   0x54
#define AT91SAM9263_AC97C_IDR                   0x58
#define AT91SAM9263_AC97C_IMR                   0x5c

  /* Serial Peripheral Interface (SPI) */
#define AT91SAM9263_SPI_SIZE                    0x40
#define AT91SAM9263_SPI_CR                      0x00
#define AT91SAM9263_SPI_MR                      0x04
#define AT91SAM9263_SPI_RDR                     0x08
#define AT91SAM9263_SPI_TDR                     0x0c
#define AT91SAM9263_SPI_SR                      0x10
#define AT91SAM9263_SPI_IER                     0x14
#define AT91SAM9263_SPI_IDR                     0x18
#define AT91SAM9263_SPI_IMR                     0x1c
#define AT91SAM9263_SPI_CSR(x)                  (0x30 + x*4)
#define AT91SAM9263_SPI_CSR0                    0x30
#define AT91SAM9263_SPI_CSR1                    0x34
#define AT91SAM9263_SPI_CSR2                    0x38
#define AT91SAM9263_SPI_CSR3                    0x3c

  /* Controller Area Network (CAN) */
#define AT91SAM9263_CAN_SIZE                    0x240
#define AT91SAM9263_CAN_MR                      0x000
#define AT91SAM9263_CAN_IER                     0x004
#define AT91SAM9263_CAN_IDR                     0x008
#define AT91SAM9263_CAN_IMR                     0x00c
#define AT91SAM9263_CAN_SR                      0x010
#define AT91SAM9263_CAN_BR                      0x014
#define AT91SAM9263_CAN_TIM                     0x018
#define AT91SAM9263_CAN_TIMESTP                 0x01c
#define AT91SAM9263_CAN_ECR                     0x020
#define AT91SAM9263_CAN_TCR                     0x024
#define AT91SAM9263_CAN_ACR                     0x028
#define AT91SAM9263_CAN_MMR(x)                  (0x200 + 0x20*x)
#define AT91SAM9263_CAN_MMR0                    0x200
#define AT91SAM9263_CAN_MAM(x)                  (0x204 + 0x20*x)
#define AT91SAM9263_CAN_MAM0                    0x204
#define AT91SAM9263_CAN_MID(x)                  (0x208 + 0x20*x)
#define AT91SAM9263_CAN_MID0                    0x208
#define AT91SAM9263_CAN_MFID(x)                 (0x20c + 0x20*x)
#define AT91SAM9263_CAN_MFID0                   0x20c
#define AT91SAM9263_CAN_MSR(x)                  (0x210 + 0x20*x)
#define AT91SAM9263_CAN_MSR0                    0x210
#define AT91SAM9263_CAN_MDL(x)                  (0x214 + 0x20*x)
#define AT91SAM9263_CAN_MDL0                    0x214
#define AT91SAM9263_CAN_MDH(x)                  (0x218 + 0x20*x)
#define AT91SAM9263_CAN_MDH0                    0x218
#define AT91SAM9263_CAN_MCR(x)                  (0x21c + 0x20*x)
#define AT91SAM9263_CAN_MCR0                    0x21c
#define AT91SAM9263_CAN_MMR1                    0x220
#define AT91SAM9263_CAN_MAM1                    0x224
#define AT91SAM9263_CAN_MID1                    0x228
#define AT91SAM9263_CAN_MFID1                   0x22c
#define AT91SAM9263_CAN_MSR1                    0x230
#define AT91SAM9263_CAN_MDL1                    0x234
#define AT91SAM9263_CAN_MDH1                    0x238
#define AT91SAM9263_CAN_MCR1                    0x23c

  /* Pulse Width Modulation (PWMC) */
#define AT91SAM9263_PWMC_SIZE                   0x234
#define AT91SAM9263_PWMC_MR                     0x000
#define AT91SAM9263_PWMC_ENA                    0x004
#define AT91SAM9263_PWMC_DIS                    0x008
#define AT91SAM9263_PWMC_SR                     0x00c
#define AT91SAM9263_PWMC_IER                    0x010
#define AT91SAM9263_PWMC_IDR                    0x014
#define AT91SAM9263_PWMC_IMR                    0x018
#define AT91SAM9263_PWMC_ISR                    0x01c
#define AT91SAM9263_PWMC_CRM0                   0x200
#define AT91SAM9263_PWMC_CRM(x)                 (0x200 + 0x20*x)
#define AT91SAM9263_PWMC_CDTY0                  0x204
#define AT91SAM9263_PWMC_CDTY(x)                (0x204 + 0x20*x)
#define AT91SAM9263_PWMC_CPRD0                  0x208
#define AT91SAM9263_PWMC_CPRD(x)                (0x208 + 0x20*x)
#define AT91SAM9263_PWMC_CCNT0                  0x20c
#define AT91SAM9263_PWMC_CCNT(x)                (0x20c + 0x20*x)
#define AT91SAM9263_PWMC_CUPD0                  0x210
#define AT91SAM9263_PWMC_CUPD(x)                (0x210 + 0x20*x)
#define AT91SAM9263_PWMC_CRM1                   0x220
#define AT91SAM9263_PWMC_CDTY1                  0x224
#define AT91SAM9263_PWMC_CPRD1                  0x228
#define AT91SAM9263_PWMC_CCNT1                  0x22c
#define AT91SAM9263_PWMC_CUPD1                  0x230

  /* Ethernet MAC (EMAC) */
#define AT91SAM9263_EMAC_SIZE                   0xc8
#define AT91SAM9263_EMAC_NCR                    0x00
#define AT91SAM9263_EMAC_NCFG                   0x04
#define AT91SAM9263_EMAC_NSR                    0x08
#define AT91SAM9263_EMAC_TSR                    0x14
#define AT91SAM9263_EMAC_RBQP                   0x18
#define AT91SAM9263_EMAC_TBQP                   0x1c
#define AT91SAM9263_EMAC_RSR                    0x20
#define AT91SAM9263_EMAC_ISR                    0x24
#define AT91SAM9263_EMAC_IER                    0x28
#define AT91SAM9263_EMAC_IDR                    0x2c
#define AT91SAM9263_EMAC_IMR                    0x30
#define AT91SAM9263_EMAC_MAN                    0x34
#define AT91SAM9263_EMAC_PTR                    0x38
#define AT91SAM9263_EMAC_PFR                    0x3c
#define AT91SAM9263_EMAC_FTO                    0x40
#define AT91SAM9263_EMAC_SCF                    0x44
#define AT91SAM9263_EMAC_MCF                    0x48
#define AT91SAM9263_EMAC_FRO                    0x4c
#define AT91SAM9263_EMAC_FCSE                   0x50
#define AT91SAM9263_EMAC_ALE                    0x54
#define AT91SAM9263_EMAC_DTF                    0x58
#define AT91SAM9263_EMAC_LCOL                   0x5c
#define AT91SAM9263_EMAC_ECOL                   0x60
#define AT91SAM9263_EMAC_TUND                   0x64
#define AT91SAM9263_EMAC_CSE                    0x68
#define AT91SAM9263_EMAC_RRE                    0x6c
#define AT91SAM9263_EMAC_ROV                    0x70
#define AT91SAM9263_EMAC_RSE                    0x74
#define AT91SAM9263_EMAC_ELE                    0x78
#define AT91SAM9263_EMAC_RJA                    0x7c
#define AT91SAM9263_EMAC_USF                    0x80
#define AT91SAM9263_EMAC_STE                    0x84
#define AT91SAM9263_EMAC_RLE                    0x88
#define AT91SAM9263_EMAC_HRB                    0x90
#define AT91SAM9263_EMAC_HRT                    0x94
#define AT91SAM9263_EMAC_SAxB(x)                (0x98 + 8*x)
#define AT91SAM9263_EMAC_SA1B                   0x98
#define AT91SAM9263_EMAC_SAxT(x)                (0x9c + 8*x)
#define AT91SAM9263_EMAC_SA1T                   0x9c
#define AT91SAM9263_EMAC_SA2B                   0xa0
#define AT91SAM9263_EMAC_SA2T                   0xa4
#define AT91SAM9263_EMAC_SA3B                   0xa8
#define AT91SAM9263_EMAC_SA3T                   0xac
#define AT91SAM9263_EMAC_SA4B                   0xb0
#define AT91SAM9263_EMAC_SA4T                   0xb4
#define AT91SAM9263_EMAC_TID                    0xb8
#define AT91SAM9263_EMAC_USRIO                  0xc0

  /* Image Sensor Interface (ISI) */
#define AT91SAM9263_ISI_SIZE                    0x44
#define AT91SAM9263_ISI_CR1                     0x00
#define AT91SAM9263_ISI_CR2                     0x04
#define AT91SAM9263_ISI_SR                      0x08
#define AT91SAM9263_ISI_IER                     0x0c
#define AT91SAM9263_ISI_IDR                     0x10
#define AT91SAM9263_ISI_IMR                     0x14
#define AT91SAM9263_ISI_PSIZE                   0x20
#define AT91SAM9263_ISI_PDECF                   0x24
#define AT91SAM9263_ISI_PPFBD                   0x28
#define AT91SAM9263_ISI_CDBA                    0x2c
#define AT91SAM9263_ISI_Y2R_SET0                0x30
#define AT91SAM9263_ISI_Y2R_SET1                0x34
#define AT91SAM9263_ISI_R2Y_SET0                0x38
#define AT91SAM9263_ISI_R2Y_SET1                0x3c
#define AT91SAM9263_ISI_R2Y_SET2                0x40

  /* 2D Graphics Controller (2DGC) */
#define AT91SAM9263_2DGC_SIZE                   0x208
#define AT91SAM9263_2DGC_BTSXR                  0x000
#define AT91SAM9263_2DGC_BTSYR                  0x004
#define AT91SAM9263_2DGC_SBXR                   0x008
#define AT91SAM9263_2DGC_SBYR                   0x00c
#define AT91SAM9263_2DGC_TEXR                   0x010
#define AT91SAM9263_2DGC_TEYR                   0x014
#define AT91SAM9263_2DGC_LWR                    0x018
#define AT91SAM9263_2DGC_LPR                    0x01c
#define AT91SAM9263_2DGC_CSR                    0x020
#define AT91SAM9263_2DGC_LOR                    0x024
#define AT91SAM9263_2DGC_GOR                    0x028
#define AT91SAM9263_2DGC_EBXR                   0x02c
#define AT91SAM9263_2DGC_EBYR                   0x030
#define AT91SAM9263_2DGC_EEXR                   0x034
#define AT91SAM9263_2DGC_EEYR                   0x038
#define AT91SAM9263_2DGC_ECSR                   0x03c
#define AT91SAM9263_2DGC_CCR                    0x040
#define AT91SAM9263_2DGC_CXMINR                 0x044
#define AT91SAM9263_2DGC_CXMAXR                 0x048
#define AT91SAM9263_2DGC_CYMINR                 0x04c
#define AT91SAM9263_2DGC_CYMAXR                 0x050
#define AT91SAM9263_2DGC_GSR                    0x054
#define AT91SAM9263_2DGC_VSR                    0x058
#define AT91SAM9263_2DGC_FCR                    0x060
#define AT91SAM9263_2DGC_GIR                    0x064
#define AT91SAM9263_2DGC_GIMR                   0x068
#define AT91SAM9263_2DGC_BPPR                   0x070
#define AT91SAM9263_2DGC_CQCR                   0x078
#define AT91SAM9263_2DGC_CQSR                   0x07c
#define AT91SAM9263_2DGC_CQR                    0x080
#define AT91SAM9263_2DGC_VXR                    0x090
#define AT91SAM9263_2DGC_VYR                    0x120
#define AT91SAM9263_2DGC_VOR                    0x200
#define AT91SAM9263_2DGC_DFR                    0x204


 /*
  * System Controller Register Declaration.
  */

  /* Error Correted Code (ECC) */
#define AT91SAM9263_ECC_SIZE                    0x14
#define AT91SAM9263_ECC_CR                      0x00
#define AT91SAM9263_ECC_MR                      0x04
#define AT91SAM9263_ECC_SR                      0x08
#define AT91SAM9263_ECC_PR                      0x0c
#define AT91SAM9263_ECC_NPR                     0x10

  /* SDRAM Controller (SDRAMC) */
#define AT91SAM9263_SDRAMC_SIZE                 0x28
#define AT91SAM9263_SDRAMC_MR                   0x00
#define AT91SAM9263_SDRAMC_TR                   0x04
#define AT91SAM9263_SDRAMC_CR                   0x08