at91sam9263.h

Centrality Atlas II development software

/*
 * $QNXLicenseC:
 * Copyright 2008, QNX Software Systems. 
 * 
 * Licensed under the Apache License, Version 2.0 (the "License"). You 
 * may not reproduce, modify or distribute this software except in 
 * compliance with the License. You may obtain a copy of the License 
 * at: http://www.apache.org/licenses/LICENSE-2.0 
 * 
 * Unless required by applicable law or agreed to in writing, software 
 * distributed under the License is distributed on an "AS IS" basis, 
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
 *
 * This file may contain contributions from others, either as 
 * contributors under the License or as licensors under other terms.  
 * Please review this entire file for other proprietary rights or license 
 * notices, as well as the QNX Development Suite License Guide at 
 * http://licensing.qnx.com/license-guide/ for other information.
 * $
 */


#ifndef _AT91SAM9263_H__
#define _AT91SAM9263_H__
/*
 * Atmel AT91SAM9263 SOC with ARM 926ES-J core.
 */


/*
* System On Chip (SOC) Memory Mapping.
*/

 /*
  * Peripheral ID Declaration and Interrupt Number.
  */
#define AT91SAM9263_ID_INUM_FIQ                 0
#define AT91SAM9263_ID_INUM_SYSC                1
#define AT91SAM9263_ID_INUM_PIOA                2
#define AT91SAM9263_ID_INUM_PIOB                3
#define AT91SAM9263_ID_INUM_PIOC                4
#define AT91SAM9263_ID_INUM_PIOD                AT91SAM9263_ID_INUM_PIOC
#define AT91SAM9263_ID_INUM_PIOE                AT91SAM9263_ID_INUM_PIOC
#define AT91SAM9263_ID_INUM_USART0              7
#define AT91SAM9263_ID_INUM_USART1              8
#define AT91SAM9263_ID_INUM_USART2              9
#define AT91SAM9263_ID_INUM_MCI0                10
#define AT91SAM9263_ID_INUM_MCI1                11
#define AT91SAM9263_ID_INUM_CAN                 12
#define AT91SAM9263_ID_INUM_TWI                 13
#define AT91SAM9263_ID_INUM_SPI0                14
#define AT91SAM9263_ID_INUM_SPI1                15
#define AT91SAM9263_ID_INUM_SSC0                16
#define AT91SAM9263_ID_INUM_SSC1                17
#define AT91SAM9263_ID_INUM_AC97C               18
#define AT91SAM9263_ID_INUM_TC0                 19
#define AT91SAM9263_ID_INUM_TC1                 AT91SAM9263_ID_INUM_TC0
#define AT91SAM9263_ID_INUM_TC2                 AT91SAM9263_ID_INUM_TC0
#define AT91SAM9263_ID_INUM_PWMC                20
#define AT91SAM9263_ID_INUM_EMAC                21
#define AT91SAM9263_ID_INUM_2DGE                23
#define AT91SAM9263_ID_INUM_UDP                 24
#define AT91SAM9263_ID_INUM_ISI                 25
#define AT91SAM9263_ID_INUM_LCDC                26
#define AT91SAM9263_ID_INUM_DMA                 27
#define AT91SAM9263_ID_INUM_UHP                 29
#define AT91SAM9263_ID_INUM_IRQ0                30
#define AT91SAM9263_ID_INUM_IRQ1                31
    
  /* Internal Memory Mapping */
#define AT91SAM9263_BOOT_BASE                   0x00000000
#define AT91SAM9263_ITCM_BASE                   0x00100000
#define AT91SAM9263_DTCM_BASE                   0x00200000
#define AT91SAM9263_SRAM_BASE                   0x00300000
#define AT91SAM9263_ROM_BASE                    0x00400000
#define AT91SAM9263_SRAM0_BASE                  0x00500000
#define AT91SAM9263_LCD_CONTROLLER_BASE         0x00700000
#define AT91SAM9263_DMAC_BASE                   0x00800000
#define AT91SAM9263_USB_HOST_BASE               0x00a00000

#define AT91SAM9263_BOOT_SIZE                   0x00100000
#define AT91SAM9263_ITCM_SIZE                   0x00100000
#define AT91SAM9263_DTCM_SIZE                   0x00100000
#define AT91SAM9263_SRAM_SIZE                   0x00100000
#define AT91SAM9263_ROM_SIZE                    0x00100000
#define AT91SAM9263_SRAM0_SIZE                  0x00100000
#define AT91SAM9263_LCD_CONTROLLER_SIZE         0x00100000
#define AT91SAM9263_DMAC_SIZE                   0x00100000
#define AT91SAM9263_USB_HOST_SIZE               0x00100000

  /* External Bus Interface 0 & 1 Mapping*/
#define AT91SAM9263_EBI0_CS0_BASE               0x10000000
#define AT91SAM9263_EBI0_CS1_BASE               0x20000000  /* SDRAMC    */
#define AT91SAM9263_EBI0_CS2_BASE               0x30000000
#define AT91SAM9263_EBI0_CS3_BASE               0x40000000  /* NANDFlash */
#define AT91SAM9263_EBI0_CS4_BASE               0x50000000  /* Compact Flash Slot 0 */
#define AT91SAM9263_EBI0_CS5_BASE               0x60000000  /* Compact Flash Slot 1 */
#define AT91SAM9263_EBI1_CS0_BASE               0x70000000
#define AT91SAM9263_EBI1_CS1_BASE               0x80000000  /* SDRAMC    */
#define AT91SAM9263_EBI1_CS2_BASE               0x90000000  /* NANDFlash */

#define AT91SAM9263_EBIX_CSX_MAX_SIZE           0x10000000  /* 256 MB           */

  /* Peripheral Mapping */
#define AT91SAM9263_UDP_BASE                    0xfff78000
#define AT91SAM9263_TC_BASE                     0xfff7c000
#define AT91SAM9263_MCI0_BASE                   0xfff80000
#define AT91SAM9263_MCI1_BASE                   0xfff84000
#define AT91SAM9263_TWI_BASE                    0xfff88000
#define AT91SAM9263_USART0_BASE                 0xfff8c000
#define AT91SAM9263_USART1_BASE                 0xfff90000
#define AT91SAM9263_USART2_BASE                 0xfff94000
#define AT91SAM9263_SSC0_BASE                   0xfff98000
#define AT91SAM9263_SSC1_BASE                   0xfff9c000
#define AT91SAM9263_AC97C_BASE                  0xfffa0000
#define AT91SAM9263_SPI0_BASE                   0xfffa4000
#define AT91SAM9263_SPI1_BASE                   0xfffa8000
#define AT91SAM9263_CAN0_BASE                   0xfffac000
#define AT91SAM9263_PWMC_BASE                   0xfffb8000
#define AT91SAM9263_EMAC_BASE                   0xfffbc000
#define AT91SAM9263_ISI_BASE                    0xfffc4000
#define AT91SAM9263_2DGC_BASE                   0xfffc8000

  /* System Controller Mapping Mapping */

#define AT91SAM9263_ECC0_BASE                   0xffffe000
#define AT91SAM9263_SDRAMC0_BASE                0xffffe200
#define AT91SAM9263_SMC0_BASE                   0xffffe400
#define AT91SAM9263_ECC1_BASE                   0xffffe600
#define AT91SAM9263_SDRAMC1_BASE                0xffffe800
#define AT91SAM9263_SMC1_BASE                   0xffffea00
#define AT91SAM9263_MATRIX_BASE                 0xffffec00
#define AT91SAM9263_CCFG_BASE                   0xffffed10
#define AT91SAM9263_DBGU_BASE                   0xffffee00
#define AT91SAM9263_AIC_BASE                    0xfffff000
#define AT91SAM9263_PIOA_BASE                   0xfffff200
#define AT91SAM9263_PIOB_BASE                   0xfffff400
#define AT91SAM9263_PIOC_BASE                   0xfffff600
#define AT91SAM9263_PIOD_BASE                   0xfffff800
#define AT91SAM9263_PIOE_BASE                   0xfffffa00
#define AT91SAM9263_PMC_BASE                    0xfffffc00
#define AT91SAM9263_RSTC_BASE                   0xfffffd00
#define AT91SAM9263_SHDWC_BASE                  0xfffffd10
#define AT91SAM9263_RTT0_BASE                   0xfffffd20
#define AT91SAM9263_PIT_BASE                    0xfffffd30
#define AT91SAM9263_WDT_BASE                    0xfffffd40
#define AT91SAM9263_RTT1_BASE                   0xfffffd50
#define AT91SAM9263_GPBR_BASE                   0xfffffd60

 /*
  * Peripheral Register Declaration.
  */

  /* USB Device Port (UDP) */
#define AT91SAM9263_UDP_SIZE                    0x100
#define AT91SAM9263_UDP_FRM_NUM                 0x00
#define AT91SAM9263_UDP_GLB_STAT                0x04
#define AT91SAM9263_UDP_FADDR                   0x08
#define AT91SAM9263_UDP_IER                     0x10
#define AT91SAM9263_UDP_IDR                     0x14
#define AT91SAM9263_UDP_IMR                     0x18
#define AT91SAM9263_UDP_ISR                     0x1c
#define AT91SAM9263_UDP_ICR                     0x20
#define AT91SAM9263_UDP_RST_EP                  0x28
#define AT91SAM9263_UDP_CSR(x)                  (0x30 + 4 * (x-1))
#define AT91SAM9263_UDP_CSR0                    0x30
#define AT91SAM9263_UDP_CSR1                    0x34
#define AT91SAM9263_UDP_CSR2                    0x38
#define AT91SAM9263_UDP_CSR3                    0x3c
#define AT91SAM9263_UDP_CSR4                    0x40
#define AT91SAM9263_UDP_CSR5                    0x44
#define AT91SAM9263_UDP_FDR(x)                  (0x50 + 4 * (x-1))
#define AT91SAM9263_UDP_FDR0                    0x50
#define AT91SAM9263_UDP_FDR1                    0x54
#define AT91SAM9263_UDP_FDR2                    0x58
#define AT91SAM9263_UDP_FDR3                    0x5c
#define AT91SAM9263_UDP_FDR4                    0x60
#define AT91SAM9263_UDP_FDR5                    0x64
#define AT91SAM9263_UDP_TXVC                    0x74

  /* Timer Counter (TC) */
#define AT91SAM9263_TC_SIZE                     0x100
#define AT91SAM9263_TC_CH(x)_OFFSET             (x * 0x40)
#define AT91SAM9263_TC_CH0                      0x00
#define AT91SAM9263_TC_CH1                      0x40
#define AT91SAM9263_TC_CH2                      0x80
#define AT91SAM9263_TC_CHx_CCR                  0x00
#define AT91SAM9263_TC_CHx_CMR                  0x04
#define AT91SAM9263_TC_CHx_CV                   0x10
#define AT91SAM9263_TC_CHx_RA                   0x14
#define AT91SAM9263_TC_CHx_RB                   0x18
#define AT91SAM9263_TC_CHx_RC                   0x1c
#define AT91SAM9263_TC_CHx_SR                   0x20
#define AT91SAM9263_TC_CHx_IER                  0x24
#define AT91SAM9263_TC_CHx_IDR                  0x28
#define AT91SAM9263_TC_CHx_IMR                  0x2c
#define AT91SAM9263_TC_BCR                      0xc0
#define AT91SAM9263_TC_BMR                      0xc4

  /* MultiMedia Card Interface (MCI) */
#define AT91SAM9263_MCI_SIZE                    0x50
#define AT91SAM9263_MCI_CR                      0x00
#define AT91SAM9263_MCI_MR                      0x04
#define AT91SAM9263_MCI_DTOR                    0x08
#define AT91SAM9263_MCI_SDCR                    0x0c
#define AT91SAM9263_MCI_ARGR                    0x10
#define AT91SAM9263_MCI_CMDR                    0x14
#define AT91SAM9263_MCI_BLKR                    0x18
#define AT91SAM9263_MCI_RSPR                    0x20
#define AT91SAM9263_MCI_RSPR_1                  0x24
#define AT91SAM9263_MCI_RSPR_2                  0x28
#define AT91SAM9263_MCI_RSPR_3                  0x2c
#define AT91SAM9263_MCI_RDR                     0x30
#define AT91SAM9263_MCI_TDR                     0x34
#define AT91SAM9263_MCI_SR                      0x40
#define AT91SAM9263_MCI_IER                     0x44
#define AT91SAM9263_MCI_IDR                     0x48
#define AT91SAM9263_MCI_IMR                     0x4c

  /* Two-wire Interface (TWI) */
#define AT91SAM9263_TWI_SIZE                    0x38
#define AT91SAM9263_TWI_CR                      0x00
#define AT91SAM9263_TWI_MMR                     0x04
#define AT91SAM9263_TWI_IADR                    0x0c
#define AT91SAM9263_TWI_CWGR                    0x10
#define AT91SAM9263_TWI_SR                      0x20
#define AT91SAM9263_TWI_IER                     0x24
#define AT91SAM9263_TWI_IDR                     0x28
#define AT91SAM9263_TWI_IMR                     0x2c
#define AT91SAM9263_TWI_RHR                     0x30
#define AT91SAM9263_TWI_THR                     0x34

  /* USART */
#define AT91SAM9263_USART_SIZE                  0x100
#define AT91SAM9263_USART_CR                    0x000
#define AT91SAM9263_USART_MR                    0x004
#define AT91SAM9263_USART_IER                   0x008
#define AT91SAM9263_USART_IDR                   0x00c
#define AT91SAM9263_USART_IMR                   0x010
#define AT91SAM9263_USART_CSR                   0x014
#define AT91SAM9263_USART_RHR                   0x018
#define AT91SAM9263_USART_THR                   0x01c
#define AT91SAM9263_USART_BRGR                  0x020
#define AT91SAM9263_USART_RTOR                  0x024
#define AT91SAM9263_USART_TTGR                  0x028
#define AT91SAM9263_USART_FIDI                  0x040 
#define AT91SAM9263_USART_NER                   0x044