sa1111.h

Centrality Atlas II development software

#define	SA1111_SASR1_RSTO       0x40000		/* Read status timeout                                   */
#define	SA1111_SASR1_CLPM       0x80000		/* Command for AC'97 Codec Low Power Mode is detected    */
#define	SA1111_SASR1_CRDY       0x100000	/* AC'97 Codec is ready for normal operation   */
#define	SA1111_SASR1_RS3V       0x200000	/* Received slot 3 is valid                    */
#define	SA1111_SASR1_RS4V       0x200000	/* Received slot 4 is valid                    */

/*
 * SA1111_SA1111_SASCR bits
 */
#define	SA1111_SASCR_TUR	0x0020		/* Clears transmit FIFO under-run status bit   */
#define	SA1111_SASCR_ROR	0x0040		/* Clears receive  FIFO overrun status bit     */
#define	SA1111_SASCR_DTS	0x10000		/* Clears L3C/AC-Link Data Sent  status bit    */
#define	SA1111_SASCR_RDD	0x20000		/* Clears L3C/AC-Link Data Read done  status bit   */
#define	SA1111_SASCR_STO	0x40000		/* Clears AC-Link Read Status Time Out  status bit */



/*
 * -------------------------------------------------------------------------
 * SSP Serial Port
 *
 * NB: values are _offsets_ from SA-1111 base address
 * -------------------------------------------------------------------------
 */

/*
 * -------------------------------------------------------------------------
 * PS/2 Trackpad and Mouse Interfaces
 *
 * NB: values are _offsets_ from SA-1111 base address
 * -------------------------------------------------------------------------
 */
#define	SA1111_PS2_TRACKPAD		0x00000a00
#define	SA1111_PS2_MOUSE		0x00000c00
#define	SA1111_PS2_SIZE			0x00000014

/*
 * Register offsets from trackpad/mouse register base
 */
#define	SA1111_KBDCR		0x00	/* Control register */
#define	SA1111_KBDSTAT		0x04	/* Status register */
#define	SA1111_KBDDATA		0x08	/* Data register */
#define	SA1111_KBDCLKDIV	0x0c	/* Clock divider register */
#define	SA1111_KBDPRECNT	0x10	/* Clock precount register */

/*
 * SA1111_KBDCR bits
 */
#define	SA1111_KBDCR_FKC	0x0001		/* Force CLK line low */
#define	SA1111_KBDCR_FKD	0x0002		/* Force DATA line low */
#define	SA1111_KBDCR_ENA	0x0008		/* Enable interface */

/*
 * SA1111_KBDSTAT bits
 */
#define	SA1111_KBDSTAT_KBC	0x0001		/* CLK pin value */
#define	SA1111_KBDSTAT_KBD	0x0002		/* DATA pin value */
#define	SA1111_KBDSTAT_RXP	0x0004		/* Parity for last received byte */
#define	SA1111_KBDSTAT_ENA	0x0008		/* Interface enabled */
#define	SA1111_KBDSTAT_RXB	0x0010		/* Rx busy */
#define	SA1111_KBDSTAT_RXF	0x0020		/* Rx register full */
#define	SA1111_KBDSTAT_TXB	0x0040		/* Tx busy */
#define	SA1111_KBDSTAT_TXE	0x0080		/* Tx register empty */
#define	SA1111_KBDSTAT_STP	0x0100		/* Stop bit error */

/*
 * SA1111_KBDCLKDIV values
 */
#define	SA1111_KBDCLKDIV_8		0		/* Divide by 8 (KbdClk is 8MHz) */
#define	SA1111_KBDCLKDIV_4		1		/* Divide by 4 (KbdClk is 4MHz) */
#define	SA1111_KBDCLKDIV_2		2		/* Divide by 2 (KbdClk is 2MHz) */

/*
 * -------------------------------------------------------------------------
 * GPIO Controller
 *
 * NB: values are _offsets_ from SA-1111 base address
 * -------------------------------------------------------------------------
 */
#define	SA1111_GPIO			0x00001000
#define	SA1111_GPIO_SIZE	0x00000030

/*
 * Register offsets from SA1111_GPIO
 */
#define	SA1111_PA_DDR	0x00		/* GPIO block A data direction */
#define	SA1111_PA_DRR	0x04		/* GPIO block A data read */
#define	SA1111_PA_DWR	0x04		/* GPIO block A data write */
#define	SA1111_PA_SDR	0x08		/* GPIO block A sleep direction */
#define	SA1111_PA_SSR	0x0c		/* GPIO Block A sleep state */
#define	SA1111_PB_DDR	0x10		/* GPIO block B data direction */
#define	SA1111_PB_DRR	0x14		/* GPIO block B data read */
#define	SA1111_PB_DWR	0x14		/* GPIO block B data write */
#define	SA1111_PB_SDR	0x18		/* GPIO block B sleep direction */
#define	SA1111_PB_SSR	0x1c		/* GPIO Block B sleep state */
#define	SA1111_PC_DDR	0x20		/* GPIO block C data direction */
#define	SA1111_PC_DRR	0x24		/* GPIO block C data read */
#define	SA1111_PC_DWR	0x24		/* GPIO block C data write */
#define	SA1111_PC_SDR	0x28		/* GPIO block C sleep direction */
#define	SA1111_PC_SSR	0x2c		/* GPIO Block C sleep state */

/*
 * -------------------------------------------------------------------------
 * Interrupt Controller
 *
 * NB: values are _offsets_ from SA-1111 base address
 * -------------------------------------------------------------------------
 */
#define	SA1111_INTR		0x00001600

/*
 * Register offsets from SA1111_INTR
 */
#define	SA1111_INTTEST0		0x00
#define	SA1111_INTTEST1		0x04
#define	SA1111_INTEN0		0x08
#define	SA1111_INTEN1		0x0c
#define	SA1111_INTPOL0		0x10
#define	SA1111_INTPOL1		0x14
#define	SA1111_INTTSTSEL	0x18
#define	SA1111_INTSTATCLR0	0x1c
#define	SA1111_INTSTATCLR1	0x20
#define	SA1111_INTSET0		0x24
#define	SA1111_INTSET1		0x28
#define	SA1111_WAKE_EN0		0x2c
#define	SA1111_WAKE_EN1		0x30
#define	SA1111_WAKE_POL0	0x34
#define	SA1111_WAKE_POL1	0x38
#define SA1111_INTR_SIZE        (SA1111_WAKE_POL1 - SA1111_INTEN0 + 4)

/*
 * SA1111 Interrupt Numbers
 */

#define SA1111_INTR_SAC_ACLINK_SENT         40
#define SA1111_INTR_SAC_ACLINK_READ_DONE    41
#define SA1111_INTR_SAC_ACLINK_READ_TIMEOUT 42


/*
 * -------------------------------------------------------------------------
 * PCMCIA Controller
 *
 * NB: values are _offsets_ from SA-1111 base address
 * -------------------------------------------------------------------------
 */
#define	SA1111_PCMCIA		0x00001800
#define	SA1111_PCMCIA_SIZE	0x0000000c

/*
 * Register offsets from SA1111_PCMCIA
 */
#define	SA1111_PCCR			0x00
#define	SA1111_PCSSR		0x04
#define	SA1111_PCSR			0x08

/*
 * SA1111_PCCR bits
 */
#define	SA1111_PCCR_S0_RST	0x0001			/* Socket 0 reset */
#define	SA1111_PCCR_S1_RST	0x0002			/* Socket 1 reset */
#define	SA1111_PCCR_S0_FLT	0x0004			/* Socket 0 float control lines */
#define	SA1111_PCCR_S1_FLT	0x0008			/* Socket 1 float control lines */
#define	SA1111_PCCR_S0_PWE	0x0010			/* Socket 0 wait enable */
#define	SA1111_PCCR_S1_PWE	0x0020			/* Socket 1 wait enable */
#define	SA1111_PCCR_S0_PSE	0x0040			/* Socket 0 5V select */
#define	SA1111_PCCR_S1_PSE	0x0080			/* Socket 1 5V select */

/*
 * SA1111_PCSR bits
 */
#define	SA1111_PCSR_S0_RDY	0x0001			/* Socket 0 RDY_nIRQ */
#define	SA1111_PCSR_S1_RDY	0x0002			/* Socket 1 RDY_nIRQ */
#define	SA1111_PCSR_S0_CD	0x0004			/* Socket 0 CD1/CD2 */
#define	SA1111_PCSR_S1_CD	0x0008			/* Socket 1 CD1/CD2 */
#define	SA1111_PCSR_S0_VS1	0x0010			/* Socket 0 VS1 */
#define	SA1111_PCSR_S0_VS2	0x0020			/* Socket 0 VS2 */
#define	SA1111_PCSR_S1_VS1	0x0040			/* Socket 1 VS1 */
#define	SA1111_PCSR_S1_VS2	0x0080			/* Socket 1 VS2 */
#define	SA1111_PCSR_S0_WP	0x0100			/* Socket 0 WP */
#define	SA1111_PCSR_S1_WP	0x0200			/* Socket 1 WP */
#define	SA1111_PCSR_S0_BVD1	0x0400			/* Socket 0 BVD1 */
#define	SA1111_PCSR_S0_BVD2	0x0800			/* Socket 0 BVD2 */
#define	SA1111_PCSR_S1_BVD1	0x1000			/* Socket 1 BVD1 */
#define	SA1111_PCSR_S1_BVD2	0x2000			/* Socket 1 BVD2 */

#endif	/* __ARM_SA1111_H_INCLUDED */

/* __SRCVERSION("sa1111.h $Rev: 169789 $"); */