callout_interrupt_omap_gpio.s

Centrality Atlas II development software

/*
 * -----------------------------------------------------------------------
 * Identify interrupt source. Bit 15 == IRQ 15 == highest priority
 *
 * Returns interrupt number in r4
 * -----------------------------------------------------------------------
 */
CALLOUT_START(interrupt_id_omap_gpio1, 0, interrupt_patch_gpio1_pri_sec)
	/*
	 * Get the GPIO interrupt controller base address (patched)
	 */
	mov		ip,     #0x000000ff
	orr		ip, ip, #0x0000ff00
	orr		ip, ip, #0x00ff0000
	orr		ip, ip, #0xff000000

	/* get primary OMAP interrupt controller base */
	mov		r0,     #0x000000ff
	orr		r0, r0, #0x0000ff00
	orr		r0, r0, #0x00ff0000
	orr		r0, r0, #0xff000000

	/* get secondary OMAP interrupt controller base */
	mov		r3,     #0x000000ff
	orr		r3, r3, #0x0000ff00
	orr		r3, r3, #0x00ff0000
	orr		r3, r3, #0xff000000

	/*
	 * read the GPIO interrupt status and mask registers,
	 * and determine the highest priority unmasked interrupt
	 */

	ldrh	r4, [ip, #OMAP_GPIO_IRQSTATUS1]
	ldrh	r5, [ip, #OMAP_GPIO_IRQENABLE1]
	and		r1, r4, r5

	/*
	 * check for glitch
	 */

	cmp		r1, #0	
	bne		1f
	mov		r4, #-1
	b		3f

1:
	mov		r4, #16
    mov     r2, #1

0:  sub     r4, r4, #1
    tst     r1, r2, lsl r4
    beq     0b

    /*
     * Mask the interrupt
     */

    mov     r2, r2, lsl r4
    strh    r2, [ip, #OMAP_GPIO_CLEAR_IRQENABLE1]

	/*
	 * clear the interrupt
	 */
	strh	r2, [ip, #OMAP_GPIO_IRQSTATUS1]

	/* hit NEW_IRQ_AGREEMENT bit on secondary */
    ldr     r1,[r3, #OMAP_INTR_CONTROL_REG]
    orr     r1, r1, #0x01
    str     r1,[r3, #OMAP_INTR_CONTROL_REG]

	/* hit NEW_IRQ_AGREEMENT bit on primary */
    ldr     r1,[r0, #OMAP_INTR_CONTROL_REG]
    orr     r1, r1, #0x01
    str     r1,[r0, #OMAP_INTR_CONTROL_REG]
3:
CALLOUT_END(interrupt_id_omap_gpio1)


/*
 * -----------------------------------------------------------------------
 * Acknowledge specified interrupt
 *
 * On entry:
 *	r4 contains the interrupt number
 *	r7 contains the interrupt mask count
 * -----------------------------------------------------------------------
 */
CALLOUT_START(interrupt_eoi_omap_gpio1, 0, interrupt_patch_gpio1)
	/*
	 * Get the interrupt controller base address (patched)
	 */
	mov		ip,     #0x000000ff
	orr		ip, ip, #0x0000ff00
	orr		ip, ip, #0x00ff0000
	orr		ip, ip, #0xff000000

    /*
     * Only unmask interrupt if mask count is zero
     */

    teq     r7, #0
    bne     0f

	mov		r2, #1
	mov		r2, r2, lsl r4	

	/*
	 * unmask interrupt
	 */
    strh    r2, [ip, #OMAP_GPIO_SET_IRQENABLE1]

0:
CALLOUT_END(interrupt_eoi_omap_gpio1)


/*
 * -----------------------------------------------------------------------
 * Mask specified interrupt
 *
 * On entry:
 *	r0 - syspage_ptr
 *	r1 - interrupt number
 *
 * Returns:
 *	r0 - error status
 * -----------------------------------------------------------------------
 */
CALLOUT_START(interrupt_mask_omap_gpio1, 0, interrupt_patch_gpio1)
	/*
	 * Get the interrupt controller base address (patched)
	 */
	mov		ip,     #0x000000ff
	orr		ip, ip, #0x0000ff00
	orr		ip, ip, #0x00ff0000
	orr		ip, ip, #0xff000000

    mov     r2, #1
    /*
     * Mask the interrupt
     */
    mov     r2, r2, lsl r1
    strh    r2, [ip, #OMAP_GPIO_CLEAR_IRQENABLE1]

    mov     r0, #0
    mov     pc, lr
CALLOUT_END(interrupt_mask_omap_gpio1)


/*
 * -----------------------------------------------------------------------
 * Unmask specified interrupt
 *
 * On entry:
 *	r0 - syspage_ptr
 *	r1 - interrupt number
 *
 * Returns:
 *	r0 - error status
 * -----------------------------------------------------------------------
 */
CALLOUT_START(interrupt_unmask_omap_gpio1, 0, interrupt_patch_gpio1)
	/*
	 * Get the interrupt controller base address (patched)
	 */
	mov		ip,     #0x000000ff
	orr		ip, ip, #0x0000ff00
	orr		ip, ip, #0x00ff0000
	orr		ip, ip, #0xff000000

    mov     r2, #1

    /*
     * Unmask the interrupt
     */
    mov     r2, r2, lsl r1
    strh    r2, [ip, #OMAP_GPIO_SET_IRQENABLE1]

	mov		r0, #0
	mov		pc, lr
CALLOUT_END(interrupt_unmask_omap_gpio1)


/*
 * -----------------------------------------------------------------------
 * Identify interrupt source. Bit 15 == IRQ 15 == highest priority
 *
 * Returns interrupt number in r4
 * -----------------------------------------------------------------------
 */
CALLOUT_START(interrupt_id_omap_mpuio, 0, interrupt_patch_mpuio_timer)
	/*
	 * Get the MPUIO interrupt controller base address (patched)
	 */
	mov		ip,     #0x000000ff
	orr		ip, ip, #0x0000ff00
	orr		ip, ip, #0x00ff0000
	orr		ip, ip, #0xff000000

	mov		r0,     #0x000000ff
	orr		r0, r0, #0x0000ff00
	orr		r0, r0, #0x00ff0000
	orr		r0, r0, #0xff000000

	/*
	 * read the MPUIO interrupt status and mask registers,
	 * and determine the highest priority unmasked interrupt
	 */
	
	/*
	 * ERRATA - reading the MPUIO_INT register when the 32 kHz clock
	 * is low or in transition can cause a lock-up of the state machine,
	 * such that further interrupts are ignored. Work-around is to poll
	 * a timer that's running off the 32kHz clock, and only read MPUIO_INT
	 * after the timer value has changed, indicating an increment.
	 * The OS timer registers have been mapped in for this purpose.
	 */


	ldr		r4, [r0, #OMAP_32KHZ_TIMER_TCR]
1:
	ldr		r5, [r0, #OMAP_32KHZ_TIMER_TCR]
	cmp		r4, r5
	beq		1b

	ldrh	r4, [ip, #OMAP_MPUIO_INT]	/* reading this register clears all ints */
	ldrh	r5, [ip, #OMAP_MPUIO_MASKIT]
	bic		r1, r4, r5

	/*
	 * check for glitch
	 */

	cmp		r1, #0	
	bne		1f
	mov		r4, #-1
	b		3f

1:
	mov		r4, #16
    mov     r2, #1

0:  sub     r4, r4, #1
    tst     r1, r2, lsl r4
    beq     0b

    /*
     * Mask the interrupt
     */

	mov     r2, r2, lsl r4
	orr		r5, r2, r5
	strh    r5, [ip, #OMAP_MPUIO_MASKIT]


3:
CALLOUT_END(interrupt_id_omap_mpuio)


/*
 * -----------------------------------------------------------------------
 * Acknowledge specified interrupt
 *
 * On entry:
 *	r4 contains the interrupt number
 *	r7 contains the interrupt mask count
 * -----------------------------------------------------------------------
 */
CALLOUT_START(interrupt_eoi_omap_mpuio, 0, interrupt_patch_mpuio)
	/*
	 * Get the interrupt controller base address (patched)
	 */
	mov		ip,     #0x000000ff
	orr		ip, ip, #0x0000ff00
	orr		ip, ip, #0x00ff0000
	orr		ip, ip, #0xff000000

    /*
     * Only unmask interrupt if mask count is zero
     */

    teq     r7, #0
    bne     0f

	mov		r2, #1
	mov		r2, r2, lsl r4	

	/*
	 * unmask interrupt
	 */

    ldrh    r1, [ip, #OMAP_MPUIO_MASKIT]
    bic     r1, r1, r2
    strh    r1, [ip, #OMAP_MPUIO_MASKIT]

0:
CALLOUT_END(interrupt_eoi_omap_mpuio)


/*
 * -----------------------------------------------------------------------
 * Mask specified interrupt
 *
 * On entry:
 *	r0 - syspage_ptr
 *	r1 - interrupt number
 *
 * Returns:
 *	r0 - error status
 * -----------------------------------------------------------------------
 */
CALLOUT_START(interrupt_mask_omap_mpuio, 0, interrupt_patch_mpuio)
	/*
	 * Get the interrupt controller base address (patched)
	 */
	mov		ip,     #0x000000ff
	orr		ip, ip, #0x0000ff00
	orr		ip, ip, #0x00ff0000
	orr		ip, ip, #0xff000000

    mov     r2, #1
    /*
     * Mask the interrupt
     */
    ldrh    r0, [ip, #OMAP_MPUIO_MASKIT]
    orr     r0, r0, r2, lsl r1
    strh    r0, [ip, #OMAP_MPUIO_MASKIT]

    mov     r0, #0
    mov     pc, lr
CALLOUT_END(interrupt_mask_omap_mpuio)


/*
 * -----------------------------------------------------------------------
 * Unmask specified interrupt
 *
 * On entry:
 *	r0 - syspage_ptr
 *	r1 - interrupt number
 *
 * Returns:
 *	r0 - error status
 * -----------------------------------------------------------------------
 */
CALLOUT_START(interrupt_unmask_omap_mpuio, 0, interrupt_patch_mpuio)
	/*
	 * Get the interrupt controller base address (patched)
	 */
	mov		ip,     #0x000000ff
	orr		ip, ip, #0x0000ff00
	orr		ip, ip, #0x00ff0000
	orr		ip, ip, #0xff000000

    mov     r2, #1

    /*
     * Unmask the interrupt
     */
    ldrh    r0, [ip, #OMAP_MPUIO_MASKIT]
    mov     r2, r2, lsl r1
    bic     r0, r0, r2
    strh    r0, [ip, #OMAP_MPUIO_MASKIT]

	mov		r0, #0
	mov		pc, lr
CALLOUT_END(interrupt_unmask_omap_mpuio)