callout_interrupt_s3c2410.s

Centrality Atlas II development software

    /*
     * Mask the interrupt
     */
    ldr     r1, [ip, #S3C2410_INTSUBMSK]
    orr     r1, r1, r2, lsl r4
    str     r1, [ip, #S3C2410_INTSUBMSK]

	/*
	 * clear the interrupt
	 */
	mov		r2, r2, lsl r4
	str     r2, [ip, #S3C2410_SUBSRCPND]
1:
CALLOUT_END(interrupt_id_s3c2410_u1)


/*
 * -----------------------------------------------------------------------
 * Acknowledge specified interrupt
 *
 * On entry:
 *	r4 contains the interrupt number
 *	r7 contains the interrupt mask count
 * -----------------------------------------------------------------------
 */
CALLOUT_START(interrupt_eoi_s3c2410_u1, 0, interrupt_patch)
	/*
	 * Get the interrupt controller base address (patched)
	 */
	mov		ip,     #0x000000ff
	orr		ip, ip, #0x0000ff00
	orr		ip, ip, #0x00ff0000
	orr		ip, ip, #0xff000000


    /*
     * Only unmask interrupt if mask count is zero
     */
    teq     r7, #0
    bne     0f

    mov     r2, #0x08

    ldr     r1, [ip, #S3C2410_INTSUBMSK]
    mov     r2, r2, lsl r4
	bic		r1, r1, r2
    str     r1, [ip, #S3C2410_INTSUBMSK]

0:
CALLOUT_END(interrupt_eoi_s3c2410_u1)


/*
 * -----------------------------------------------------------------------
 * Mask specified interrupt
 *
 * On entry:
 *	r0 - syspage_ptr
 *	r1 - interrupt number
 *
 * Returns:
 *	r0 - error status
 * -----------------------------------------------------------------------
 */
CALLOUT_START(interrupt_mask_s3c2410_u1, 0, interrupt_patch)
	/*
	 * Get the interrupt controller base address (patched)
	 */
	mov		ip,     #0x000000ff
	orr		ip, ip, #0x0000ff00
	orr		ip, ip, #0x00ff0000
	orr		ip, ip, #0xff000000

    mov     r2, #0x08

    /*
     * Mask the interrupt
     */
    ldr     r3, [ip, #S3C2410_INTSUBMSK]
    orr     r3, r3, r2, lsl r1
    str     r3, [ip, #S3C2410_INTSUBMSK]
    mov     r0, #0
    mov     pc, lr
CALLOUT_END(interrupt_mask_s3c2410_u1)


/*
 * -----------------------------------------------------------------------
 * Unmask specified interrupt
 *
 * On entry:
 *	r0 - syspage_ptr
 *	r1 - interrupt number
 *
 * Returns:
 *	r0 - error status
 * -----------------------------------------------------------------------
 */
CALLOUT_START(interrupt_unmask_s3c2410_u1, 0, interrupt_patch)
	/*
	 * Get the interrupt controller base address (patched)
	 */
	mov		ip,     #0x000000ff
	orr		ip, ip, #0x0000ff00
	orr		ip, ip, #0x00ff0000
	orr		ip, ip, #0xff000000

    mov     r2, #0x08

    /*
     * Unmask the interrupt
     */
    ldr     r3, [ip, #S3C2410_INTSUBMSK]
	mov		r2, r2, lsl r1
    bic     r3, r3, r2
    str     r3, [ip, #S3C2410_INTSUBMSK]
	mov		r0, #0
	mov		pc, lr
CALLOUT_END(interrupt_unmask_s3c2410_u1)

/*
 * -----------------------------------------------------------------------
 * Identify interrupt source.
 *
 * Returns interrupt number in r4
 * -----------------------------------------------------------------------
 */
CALLOUT_START(interrupt_id_s3c2410_u2, 0, interrupt_patch)
	/*
	 * Get the interrupt controller base address (patched)
	 */
	mov		ip,     #0x000000ff
	orr		ip, ip, #0x0000ff00
	orr		ip, ip, #0x00ff0000
	orr		ip, ip, #0xff000000

	mov		r4, #-1

    /*
     * Read pending IRQ interrupts - check only positions 6, 7, and 8 (UART 2 ints)
     */
    ldr     r1, [ip, #S3C2410_SUBSRCPND]
    ldr     r2, [ip, #S3C2410_INTSUBMSK]
    bic     r1, r1, r2

	cmp		r1, #0
	beq		1f

    mov     r4, #3
    mov     r2, #0x40

    /*
     * Scan for first set bit
     */
0:  subs    r4, r4, #1
    blt     1f
    tst     r1, r2, lsl r4
    beq     0b

    /*
     * Mask the interrupt
     */
    ldr     r1, [ip, #S3C2410_INTSUBMSK]
    orr     r1, r1, r2, lsl r4
    str     r1, [ip, #S3C2410_INTSUBMSK]

	/*
	 * clear the interrupt
	 */
	mov		r2, r2, lsl r4
	str     r2, [ip, #S3C2410_SUBSRCPND]
1:
CALLOUT_END(interrupt_id_s3c2410_u2)


/*
 * -----------------------------------------------------------------------
 * Acknowledge specified interrupt
 *
 * On entry:
 *	r4 contains the interrupt number
 *	r7 contains the interrupt mask count
 * -----------------------------------------------------------------------
 */
CALLOUT_START(interrupt_eoi_s3c2410_u2, 0, interrupt_patch)
	/*
	 * Get the interrupt controller base address (patched)
	 */
	mov		ip,     #0x000000ff
	orr		ip, ip, #0x0000ff00
	orr		ip, ip, #0x00ff0000
	orr		ip, ip, #0xff000000


    /*
     * Only unmask interrupt if mask count is zero
     */
    teq     r7, #0
    bne     0f

    mov     r2, #0x40

    ldr     r1, [ip, #S3C2410_INTSUBMSK]
    mov     r2, r2, lsl r4
	bic		r1, r1, r2
    str     r1, [ip, #S3C2410_INTSUBMSK]

0:
CALLOUT_END(interrupt_eoi_s3c2410_u2)


/*
 * -----------------------------------------------------------------------
 * Mask specified interrupt
 *
 * On entry:
 *	r0 - syspage_ptr
 *	r1 - interrupt number
 *
 * Returns:
 *	r0 - error status
 * -----------------------------------------------------------------------
 */
CALLOUT_START(interrupt_mask_s3c2410_u2, 0, interrupt_patch)
	/*
	 * Get the interrupt controller base address (patched)
	 */
	mov		ip,     #0x000000ff
	orr		ip, ip, #0x0000ff00
	orr		ip, ip, #0x00ff0000
	orr		ip, ip, #0xff000000

    mov     r2, #0x40

    /*
     * Mask the interrupt
     */
    ldr     r3, [ip, #S3C2410_INTSUBMSK]
    orr     r3, r3, r2, lsl r1
    str     r3, [ip, #S3C2410_INTSUBMSK]
    mov     r0, #0
    mov     pc, lr
CALLOUT_END(interrupt_mask_s3c2410_u2)


/*
 * -----------------------------------------------------------------------
 * Unmask specified interrupt
 *
 * On entry:
 *	r0 - syspage_ptr
 *	r1 - interrupt number
 *
 * Returns:
 *	r0 - error status
 * -----------------------------------------------------------------------
 */
CALLOUT_START(interrupt_unmask_s3c2410_u2, 0, interrupt_patch)
	/*
	 * Get the interrupt controller base address (patched)
	 */
	mov		ip,     #0x000000ff
	orr		ip, ip, #0x0000ff00
	orr		ip, ip, #0x00ff0000
	orr		ip, ip, #0xff000000

    mov     r2, #0x40

    /*
     * Unmask the interrupt
     */
    ldr     r3, [ip, #S3C2410_INTSUBMSK]
	mov		r2, r2, lsl r1
    bic     r3, r3, r2
    str     r3, [ip, #S3C2410_INTSUBMSK]
	mov		r0, #0
	mov		pc, lr
CALLOUT_END(interrupt_unmask_s3c2410_u2)

/*
 * -----------------------------------------------------------------------
 * Identify interrupt source.
 *
 * Returns interrupt number in r4
 * -----------------------------------------------------------------------
 */
CALLOUT_START(interrupt_id_s3c2410_adc_tc, 0, interrupt_patch)
	/*
	 * Get the interrupt controller base address (patched)
	 */
	mov		ip,     #0x000000ff
	orr		ip, ip, #0x0000ff00
	orr		ip, ip, #0x00ff0000
	orr		ip, ip, #0xff000000


	mov		r4, #-1
    /*
     * Read pending IRQ interrupts - check only positions 9 and 10 (ADC and touch controller ints)
     */
    ldr     r1, [ip, #S3C2410_SUBSRCPND]
    ldr     r2, [ip, #S3C2410_INTSUBMSK]
    bic     r1, r1, r2

	cmp		r1, #0
	beq		1f

    mov     r4, #2
    mov     r2, #0x200

    /*
     * Scan for first set bit
     */
0:  subs    r4, r4, #1
    blt     1f
    tst     r1, r2, lsl r4
    beq     0b

    /*
     * Mask the interrupt
     */
    ldr     r1, [ip, #S3C2410_INTSUBMSK]
    orr     r1, r1, r2, lsl r4
    str     r1, [ip, #S3C2410_INTSUBMSK]

	/*
	 * clear the interrupt
	 */
	mov		r2, r2, lsl r4
	str     r2, [ip, #S3C2410_SUBSRCPND]
1:
CALLOUT_END(interrupt_id_s3c2410_adc_tc)


/*
 * -----------------------------------------------------------------------
 * Acknowledge specified interrupt
 *
 * On entry:
 *	r4 contains the interrupt number
 *	r7 contains the interrupt mask count
 * -----------------------------------------------------------------------
 */
CALLOUT_START(interrupt_eoi_s3c2410_adc_tc, 0, interrupt_patch)
	/*
	 * Get the interrupt controller base address (patched)
	 */
	mov		ip,     #0x000000ff
	orr		ip, ip, #0x0000ff00
	orr		ip, ip, #0x00ff0000
	orr		ip, ip, #0xff000000


    /*
     * Only unmask interrupt if mask count is zero
     */
    teq     r7, #0
    bne     0f

    mov     r2, #0x200

    ldr     r1, [ip, #S3C2410_INTSUBMSK]
    mov     r2, r2, lsl r4
	bic		r1, r1, r2
    str     r1, [ip, #S3C2410_INTSUBMSK]

0:
CALLOUT_END(interrupt_eoi_s3c2410_adc_tc)


/*
 * -----------------------------------------------------------------------
 * Mask specified interrupt
 *
 * On entry:
 *	r0 - syspage_ptr
 *	r1 - interrupt number
 *
 * Returns:
 *	r0 - error status
 * -----------------------------------------------------------------------
 */
CALLOUT_START(interrupt_mask_s3c2410_adc_tc, 0, interrupt_patch)
	/*
	 * Get the interrupt controller base address (patched)
	 */
	mov		ip,     #0x000000ff
	orr		ip, ip, #0x0000ff00
	orr		ip, ip, #0x00ff0000
	orr		ip, ip, #0xff000000

    mov     r2, #0x200

    /*
     * Mask the interrupt
     */
    ldr     r3, [ip, #S3C2410_INTSUBMSK]
    orr     r3, r3, r2, lsl r1
    str     r3, [ip, #S3C2410_INTSUBMSK]
    mov     r0, #0
    mov     pc, lr
CALLOUT_END(interrupt_mask_s3c2410_adc_tc)


/*
 * -----------------------------------------------------------------------
 * Unmask specified interrupt
 *
 * On entry:
 *	r0 - syspage_ptr
 *	r1 - interrupt number
 *
 * Returns:
 *	r0 - error status
 * -----------------------------------------------------------------------
 */
CALLOUT_START(interrupt_unmask_s3c2410_adc_tc, 0, interrupt_patch)
	/*
	 * Get the interrupt controller base address (patched)
	 */
	mov		ip,     #0x000000ff
	orr		ip, ip, #0x0000ff00
	orr		ip, ip, #0x00ff0000
	orr		ip, ip, #0xff000000

    mov     r2, #0x200

    /*
     * Unmask the interrupt
     */
    ldr     r3, [ip, #S3C2410_INTSUBMSK]
	mov		r2, r2, lsl r1
    bic     r3, r3, r2
    str     r3, [ip, #S3C2410_INTSUBMSK]
	mov		r0, #0
	mov		pc, lr
CALLOUT_END(interrupt_unmask_s3c2410_adc_tc)