📄 display.h
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/* Valid alpha combinations */#define DISP_ALPHA_CAP_SPP_WITH_GLOBAL 0x00000001 /* Source Per-pixel with Dest global supported */#define DISP_ALPHA_CAP_GLOBAL_WITH_DPP 0x00000002 /* Source global with Dest Per-pixel supported */#define DISP_ALPHA_CAP_SPP_WITH_DPP 0x00000004 /* Source per-pixel with Dest per-pixel supported */#define DISP_ALPHA_CAP_GLOBAL_WITH_GLOBAL 0x00000008 /* Source global with Dest global supported */#define DISP_ALPHA_BLEND_CAP_SPP_WITH_GLOBAL DISP_ALPHA_CAP_SPP_WITH_GLOBAL#define DISP_ALPHA_BLEND_CAP_GLOBAL_WITH_DPP DISP_ALPHA_CAP_GLOBAL_WITH_DPP#define DISP_ALPHA_BLEND_CAP_SPP_WITH_DPP DISP_ALPHA_CAP_SPP_WITH_DPP#define DISP_ALPHA_BLEND_CAP_GLOBAL_WITH_GLOBAL DISP_ALPHA_CAP_GLOBAL_WITH_GLOBAL/* Chroma Key operations */#define DISP_CHROMA_OP_SRC_MATCH 0x00000001 /* Match Color is Source Color */#define DISP_CHROMA_OP_DST_MATCH 0x00000002 /* Match Color is Destination Color */#define DISP_CHROMA_OP_DRAW 0x00000004 /* if Match Color == Color, Draw */#define DISP_CHROMA_OP_NO_DRAW 0x00000008 /* if Match Color == Color, Don't Draw */#define DISP_CHROMA_OP_UNDEFINED ~(DISP_CHROMA_OP_SRC_MATCH | \ DISP_CHROMA_OP_DST_MATCH | \ DISP_CHROMA_OP_DRAW | \ DISP_CHROMA_OP_NO_DRAW)typedef uint32_t disp_color_t;typedef struct { int32_t x; int32_t y;} disp_point_t;typedef int disp_fx_t; /* Fixed point: S1:I15:F16 */#define DISP_ADD_FUNC(tabletype, table, entry, func, limit) \ if (((size_t)&(((tabletype *)0)->entry)) + sizeof (void (*)()) <= (size_t)(limit)) \ (table)->entry = (func);/* disp_adapter.caps */#define DISP_CAP_MULTI_MONITOR_SAFE 0x00000001#define DISP_CAP_2D_ACCEL 0x00000002#define DISP_CAP_3D_ACCEL 0x00000004#define DISP_CAP_NO_IO_PRIVITY 0x00000008 /* 2D/3D entry points can be called without I/O privity */#define DISP_CAP_DYNAMIC_MODESWITCH 0x00000010 /* Display modeswitches can occur without damaging any surfaces, or disturbing the layer state *//* disp_adapter.bus_type */#define DISP_BUS_TYPE_UNKNOWN 0x00000000#define DISP_BUS_TYPE_PCI 0x00000001#define DISP_BUS_TYPE_AGP 0x00000002#define DISP_BUS_TYPE_ISA 0x00000004#define DISP_BUS_TYPE_VL 0x00000010#define DISP_BUS_TYPE_IS_PCI_OR_AGP(__type) ((__type) & (DISP_BUS_TYPE_PCI|DISP_BUS_TYPE_AGP))#define DISP_PADDR_INVALID (~(disp_paddr_t)0)/* Commands for disp_adapter_t.callback */#define DISP_CALLBACK_LOCK 1#define DISP_CALLBACK_UNLOCK 2#define DISP_CALLBACK_WAIT_IDLE 3#define DISP_CALLBACK_ALLOC_SURFACE 4#define DISP_CALLBACK_FREE_SURFACE 5#define DISP_CALLBACK_WAIT_VSYNC 6typedef struct disp_adapter { int size; /* size of structure */ void *gd_ctx; /* graphics drivers private context */ void *ms_ctx; /* Mode-switchers private context */ void *mm_ctx; /* Memory-managers private context */ void *vid_ctx; /* Video Overlay drivers private context */ void *vcap_ctx; /* Video Capture drivers private context */ void * (*callback)(void *handle, unsigned cmd, void *data); void *callback_handle; volatile unsigned *vsync_counter; void *display_update_mutex; uintptr_t reserved; void **hook_context; int hook_index; int irq; /* Devices irq, set by disp_pci_init; -1 if unable to generate interrupts */ uintptr_t reserved1[2]; int bus_type; union { struct {#ifdef __QNXNTO__ int pci_handle; /* Used internally by disputil */ void *pci_dev_handle; /* Used internally by disputil */#else unsigned pci_bus; /* Used internally by disputil */ unsigned pci_devfunc; /* Used internally by disputil */#endif unsigned short pci_vendor_id; /* Devices PCI vendor ID (0 if not applicable) */ unsigned short pci_device_id; /* Devices PCI device ID */ short pci_index; /* Together, {pci_vendor_id, pci_deviceid, pci_index} uniquely identify a PCI device in the system */#ifdef __QNXNTO__ struct pci_dev_info *dev_info;#else uintptr_t reserved; /* Current flags to pass to pci_attach */#endif disp_paddr_t base[6]; /* devices PCI aperture base addresses; set by disp_pci_init */ disp_paddr_t apsize[6]; /* size of PCI apertures; set by disp_pci_init */ } pci; struct { unsigned reserved1; unsigned reserved2; unsigned short vendor_id; /* Devices vendor ID (0 if not applicable) */ unsigned short device_id; /* Devices device ID */ short index; /* Together, {vendor_id, deviceid, index} uniquely identify a device in the system */ } generic; } bus; unsigned caps; /* Adapter capabilities */ FILE *dbgfile; /* Debug sent here if non-NULL */ uintptr_t reserved2; /* interrupts the card can generate */ uintptr_t reserved3; void *shmem; void *hydra_shmem; /* For multi-monitor support */ struct disp_modefuncs *modefuncs; struct disp_memfuncs *memfuncs; int adapter_ram; /* Total memory installed on the adapter */#if !defined(__QNXNTO__) || defined (__X86__) struct vbios_context *vbios;#else uintptr_t reservedv;#endif void *ffb_extension; int pulseprio; uintptr_t reserved4[2]; unsigned cbsize; /* permanetly allocated video capture buffer size */ unsigned dflags; /* debug flags */} disp_adapter_t;/* Constants for filling in the disp_module_info structure */#define DDK_VERSION_MAJOR 1#define DDK_VERSION_MINOR 2#define DDK_REVISION 0typedef struct disp_module_info { uint8_t ddk_version_major; /* Major version of DDK used to build driver */ uint8_t ddk_version_minor; /* Minor version of DDK used to build driver */ uint8_t ddk_rev; /* Rev. of DDK used to build driver */ uint8_t driver_rev; /* Driver revision number */ char *description; unsigned reserved[16];} disp_module_info_t;/* Flags for memory management */#define DISP_PROT_READ (PROT_READ)#define DISP_PROT_WRITE (PROT_WRITE)#define DISP_PROT_NOCACHE (PROT_NOCACHE)#ifdef __QNXNTO__#define DISP_MAP_PHYS (MAP_PHYS)#define DISP_MAP_BELOW16M (MAP_BELOW16M)#define DISP_MAP_LAZY (MAP_LAZY)#else#define DISP_MAP_PHYS 0x00010000 /* Get physically contiguous RAM */#define DISP_MAP_BELOW16M 0x00040000 /* Get RAM that is physically below 16 Meg */#define DISP_MAP_LAZY 0x00000080 /* Map with write combining (or equivalent caching policy; processor dependant) */#endif/* disp_surface.flags *//* Surface capabilities flags */#define DISP_SURFACE_DISPLAYABLE 0x00000001 /* Surface can be displayed via CRT controller */ #define DISP_SURFACE_CPU_LINEAR_READABLE 0x00000002 /* CPU can read this surface directly */#define DISP_SURFACE_CPU_LINEAR_WRITEABLE 0x00000004 /* CPU can write to this surface directly */#define DISP_SURFACE_2D_READABLE 0x00000008 /* surface is read-accessible by 2D engine */#define DISP_SURFACE_3D_READABLE 0x00000010 /* surface is read-accessible by 3D engine */#define DISP_SURFACE_2D_TARGETABLE 0x00000020 /* 2D engine can render into surface */#define DISP_SURFACE_3D_TARGETABLE 0x00000040 /* 3D engine can render into surface */#define DISP_SURFACE_SCALER_DISPLAYABLE 0x00000080 /* Surface can be displayed via video overlay scaler */#define DISP_SURFACE_VMI_TARGETABLE 0x00000100 /* Video in hardware can write frames into surface */#define DISP_SURFACE_DMA_SAFE 0x00000200 /* DMA engine can treat the surface memory as one contiguous block */#define DISP_SURFACE_PAGE_ALIGNED 0x00000400 /* Surface memory starts on a page boundary, and its linear size is a multiple of the page size */#define DISP_SURFACE_BYTES_REVERSED 0x00001000 /* Byte order is reversed. Only valid for 16 and 32bpp surfaces */#define DISP_SURFACE_OTHER_ENDIAN 0x00001000 /* Obsolete - use DISP_SURFACE_BIG_ENDIAN */#define DISP_SURFACE_NON_CACHEABLE 0x00002000 /* Memory should be mapped non-cachable */#define DISP_SURFACE_WT_CACHEABLE 0x00004000 /* Memory can be mapped write-through cacheable (but not write-back cacheable) */#define DISP_SURFACE_PHYS_CONTIG 0x00008000 /* Memory is physically contiguous */#define DISP_SURFACE_DRIVER_NOT_OWNER 0x00010000 /* Driver did not create/allocate this surface (e.g. images coming from higher-level software) */#define DISP_SURFACE_ALPHA_MAP 0x00020000 /* Surface can be used as an alpha map for rendering */#define DISP_SURFACE_RECT 0x00040000#define DISP_SURFACE_STRIDE_ALIGNED 0x00080000#define DISP_SURFACE_DRIVER_PRIVATE 0x00100000 /* Has surface been specially mapped for the given process *//* Hint flags - mutually exclusive */#define DISP_SURFACE_SLOW_CPU_ACCESS 0x80000000 /* Surface memory access by CPU is expensive */#define DISP_SURFACE_SLOW_2D_ENGINE_ACCESS 0x40000000 /* Surface memory access by 2D engine is expensive */#define DISP_SURFACE_SLOW_3D_ENGINE_ACCESS 0x40000000 /* Surface memory access by 3D engine is expensive */#define DISP_SURFACE_ZONE_MASK 0x0f000000#define DISP_SURFACE_ZONE_SHIFT 24#define DISP_SURFACE_CAPS_MASK 0x00fffffftypedef uint8_t* ch_address;typedef struct disp_surface { int size; /* Size of this struct */ unsigned pixel_format; unsigned offset; /* device-dependent address */ unsigned char *vidptr; /* virtual address */ disp_paddr_t paddr; /* physical address */ unsigned stride; /* In bytes */ unsigned flags; /* Surface flags */ int width; /* In pixels */ int height; disp_color_t *palette; /* palette associated with this surface, if any */ int palette_valid_entries; /* size of palette */ disp_adapter_t *adapter; /* the adapter which created this surface (if any) */ ch_address **buffer; /* double index for surface buffer */ uintptr_t driver_private; uintptr_t reserved[7];} disp_surface_t;#ifdef DISP_DEBUG/* * This assert deliberately causes a fault upon failure, so that you can * obtain a core dump of the process at the time of the assertion failure */#define DISP_ASSERT(x) if (!(x)) { \ fprintf(stderr, \ "%s, line %d: assert failed: %s\n", \ __FILE__, __LINE__, #x); \ (*(char * volatile)0)++; \ }#else#define DISP_ASSERT(x)#endif#ifndef _GRAPHICS_VMEM_H_INCLUDED#include <graphics/vmem.h>#endif#ifndef _GRAPHICS_DRAW_H_INCLUDED#include <graphics/draw.h>#endif#ifndef _GRAPHICS_MODE_H_INCLUDED#include <graphics/mode.h>#endif#ifndef _GRAPHICS_VID_H_INCLUDED#include <graphics/vid.h>#endif#ifndef _GRAPHICS_VCAP_H_INCLUDED#include <graphics/vcap.h>#endif#ifndef _GRAPHICS_DINLINE_H_INCLUDED#include <graphics/dinline.h>#endif#ifndef _GRAPHICS_FIXED_H_INCLUDED#include <graphics/fixed.h>#endif__BEGIN_DECLSextern int devg_hook_fini(disp_adapter_t *adapter);__END_DECLS#endif /* _GRAPHICS_DISPLAY_H_INCLUDED */
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