📄 st39vf040.lst
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<
< .DEFINE C_DAC1_DIRECT 0x0000 // P_DAC_Ctrl
< .DEFINE C_DAC1_LATCH_A 0x0080 // P_DAC_Ctrl
< .DEFINE C_DAC1_LATCH_B 0x0100 // P_DAC_Ctrl
< .DEFINE C_DAC1_LATCH_AB 0x0180 // P_DAC_Ctrl
< .DEFINE C_DAC2_DIRECT 0x0000 // P_DAC_Ctrl
< .DEFINE C_DAC2_LATCH_A 0x0020 // P_DAC_Ctrl
< .DEFINE C_DAC2_LATCH_B 0x0040 // P_DAC_Ctrl
< .DEFINE C_DAC2_LATCH_AB 0x0060 // P_DAC_Ctrl
< .DEFINE C_MIC_DIRECT 0x0000 // P_DAC_Ctrl
< .DEFINE C_MIC_LATCH_A 0x0008 // P_DAC_Ctrl
< .DEFINE C_MIC_LATCH_B 0x0010 // P_DAC_Ctrl
< .DEFINE C_MIC_LATCH_AB 0x0018 // P_DAC_Ctrl
< .DEFINE C_DAC_DIS 0x0002 // P_DAC_Ctrl
<
< // Constants for SIO
< .DEFINE C_SIO_CONFIG 0x0080 // P_SIO_Ctrl
< .DEFINE C_SIO_READ 0x0000 // P_SIO_Ctrl
< .DEFINE C_SIO_WRITE 0x0040 // P_SIO_Ctrl
< .DEFINE C_SIO_CLOCK_32 0x0018 // P_SIO_Ctrl
< .DEFINE C_SIO_CLOCK_16 0x0000 // P_SIO_Ctrl
< .DEFINE C_SIO_CLOCK_8 0x0010 // P_SIO_Ctrl
< .DEFINE C_SIO_ADDR_24 0x0003 // P_SIO_Ctrl
< .DEFINE C_SIO_ADDR_16 0x0000 // P_SIO_Ctrl
< .DEFINE C_SIO_ADDR_8 0x0002 // P_SIO_Ctrl
< .DEFINE C_SIO_ADDR_NO 0x0001 // P_SIO_Ctrl
<
< .DEFINE C_SIO_BUSY 0x0080 // P_SIO_Start
<
< // Constants for UART
< .DEFINE C_UART_RX_INT 0x0080 // P_UART_Command1
< .DEFINE C_UART_TX_INT 0x0040 // P_UART_Command1
< .DEFINE C_UART_RESET 0x0020 // P_UART_Command1
< .DEFINE C_UART_PARITY_EVEN 0x0008 // P_UART_Command1
< .DEFINE C_UART_PARITY_ODD 0x0000 // P_UART_Command1
< .DEFINE C_UART_PARITY_EN 0x0004 // P_UART_Command1
< .DEFINE C_UART_PARITY_DIS 0x0000 // P_UART_Command1
<
< .DEFINE C_UART_RX_RDY 0x0080 // P_UART_Command2
< .DEFINE C_UART_TX_RDY 0x0040 // P_UART_Command2
< .DEFINE C_UART_RX_EN 0x0080 // P_UART_Command2
< .DEFINE C_UART_TX_EN 0x0040 // P_UART_Command2
< .DEFINE C_UART_PE 0x0008 // P_UART_Command2
< .DEFINE C_UART_OE 0x0010 // P_UART_Command2
< .DEFINE C_UART_FE 0x0020 // P_UART_Command2
<
< // Constants for Feedback
< .DEFINE C_FEEDBACK1_EN 0x0004 // P_Feedback
< .DEFINE C_FEEDBACK2_EN 0x0008 // P_Feedback
< .DEFINE C_IRTX_EN 0x0001 // P_Feedback
<
< // Constants for LVD
< .DEFINE C_LVD33V 0x0002 // P_LVD_Ctrl
< .DEFINE C_LVD29V 0x0001 // P_LVD_Ctrl
<
< // Other Constants
< .DEFINE C_WDTCLR 0x0001 // P_Watchdog_Clear
<
< ///////////////////////////////////////////////////////////////////
< // Old definitions for LVD @'hardware.inc'
< .DEFINE C_LVD24V 0x0000 // P_LVD_Ctrl
< .DEFINE C_LVD28V 0x0001 // P_LVD_Ctrl
< .DEFINE C_LVD32V 0x0002 // P_LVD_Ctrl
< .DEFINE C_LVD36V 0x0003 // P_LVD_Ctrl
<
< // Old definitions for TimerA & TimerB @'hardware.inc'
< .DEFINE C_Fosc_2 0x0000 // P_TimerA_Ctrl
< .DEFINE C_Fosc_256 0x0001 // P_TimerA_Ctrl
< .DEFINE C_32768Hz 0x0002 // P_TimerA_Ctrl
< .DEFINE C_8192Hz 0x0003 // P_TimerA_Ctrl
< .DEFINE C_4096Hz 0x0004 // P_TimerA_Ctrl
< .DEFINE C_A1 0x0005 // P_TimerA_Ctrl
< .DEFINE C_A0 0x0006 // P_TimerA_Ctrl
< .DEFINE C_Ext1 0x0007 // P_TimerA_Ctrl
<
< .DEFINE C_2048Hz 0x0000 // P_TimerA_Ctrl, P_TimerB_Ctrl
< .DEFINE C_1024Hz 0x0008 // P_TimerA_Ctrl, P_TimerB_Ctrl
< .DEFINE C_256Hz 0x0010 // P_TimerA_Ctrl, P_TimerB_Ctrl
< .DEFINE C_TMB1Hz 0x0018 // P_TimerA_Ctrl, P_TimerB_Ctrl
< .DEFINE C_4Hz 0x0020 // P_TimerA_Ctrl, P_TimerB_Ctrl
< .DEFINE C_2Hz 0x0028 // P_TimerA_Ctrl, P_TimerB_Ctrl
< .DEFINE C_B1 0x0030 // P_TimerA_Ctrl, P_TimerB_Ctrl
< .DEFINE C_Ext2 0x0038 // P_TimerA_Ctrl, P_TimerB_Ctrl
<
< .DEFINE C_Off 0x0000 // P_TimerA_Ctrl, P_TimerB_Ctrl
< .DEFINE C_D1 0x0040 // P_TimerA_Ctrl, P_TimerB_Ctrl
< .DEFINE C_D2 0x0080 // P_TimerA_Ctrl, P_TimerB_Ctrl
< .DEFINE C_D3 0x00C0 // P_TimerA_Ctrl, P_TimerB_Ctrl
< .DEFINE C_D4 0x0100 // P_TimerA_Ctrl, P_TimerB_Ctrl
< .DEFINE C_D5 0x0140 // P_TimerA_Ctrl, P_TimerB_Ctrl
< .DEFINE C_D6 0x0180 // P_TimerA_Ctrl, P_TimerB_Ctrl
< .DEFINE C_D7 0x01C0 // P_TimerA_Ctrl, P_TimerB_Ctrl
< .DEFINE C_D8 0x0200 // P_TimerA_Ctrl, P_TimerB_Ctrl
< .DEFINE C_D9 0x0240 // P_TimerA_Ctrl, P_TimerB_Ctrl
< .DEFINE C_D10 0x0280 // P_TimerA_Ctrl, P_TimerB_Ctrl
< .DEFINE C_D11 0x02C0 // P_TimerA_Ctrl, P_TimerB_Ctrl
< .DEFINE C_D12 0x0300 // P_TimerA_Ctrl, P_TimerB_Ctrl
< .DEFINE C_D13 0x0340 // P_TimerA_Ctrl, P_TimerB_Ctrl
< .DEFINE C_D14 0x0380 // P_TimerA_Ctrl, P_TimerB_Ctrl
< .DEFINE C_TA_Div_2 0x03C0 // P_TimerA_Ctrl
< .DEFINE C_TB_Div_2 0x03C0 // P_TimerB_Ctrl
<
< //========================================================================================
< // End of SPCE061A.inc
< //========================================================================================
.DEFINE AE_BIT_DIS 0x1000
.DEFINE RE_BIT_DIS 0x2000
.DEFINE WE_BIT_DIS 0x4000
.DEFINE CE_BIT_DIS 0x8000
//////////////////////////////////////////////
//ST39VF040 command
/////////////////////////////////////////////
0000970C .data
0000970C 55 55 AA 2A Software_bytewrite_addr: .dw 0x5555,0x2aaa,0x5555
55 55
0000970F AA 00 55 00 Software_bytewrite_data: .dw 0x00aa,0x0055,0x00a0
A0 00
00009712 55 55 AA 2A Software_chiperase_addr: .dw 0x5555,0x2aaa,0x5555,0x5555,0x2aaa,0x5555
55 55 55 55
AA 2A 55 55
00009718 AA 00 55 00 Software_chiperase_data: .dw 0x00aa,0x0055,0x0080,0x00aa,0x0055,0x0010
80 00 AA 00
55 00 10 00
0000971E 55 55 AA 2A Software_sectorerase_addr: .dw 0x5555,0x2aaa,0x5555,0x5555,0x2aaa
55 55 55 55
AA 2A
00009723 AA 00 55 00 Software_sectorerase_data: .dw 0x00aa,0x0055,0x0080,0x00aa,0x0055
80 00 AA 00
55 00
000001FB .IRAM
000001FB 00 00 .VAR Read_Byte=0
000001FC 00 00 .VAR Read_Byte2=0
000001FD 00 00 .VAR Write_Byte=0
.PUBLIC _ERASE_ST39VF040
.PUBLIC _ERASE_ST39VF040_Sector
.PUBLIC _Write_ST39VF040_One_Word
.PUBLIC _Read_ST39VF040_One_Word
00009461 .CODE
//----------------------------------------------------------------------
_ERASE_ST39VF040_Sector:
00009461 88 DA PUSH bp TO [SP]
00009462 00 9B R5 = SP
00009463 04 98 R4 = [R5 + 4] //get AddrL
00009464 40 9A R5 = 0x0000
Chip_SectorErase:
00009465 0D 03 1E 97 R1 = R5 + Software_sectorerase_addr
00009467 0D 07 23 97 R3 = R5 + Software_sectorerase_data
00009469 C1 92 R1 = [R1] //get LOW address
0000946A C3 96 R3 = [R3] //get data
0000946B 40 94 R2 = 0x0000 //get HIGH address
0000946C 40 F0 BF 94 call Write_ST39VF040_One_Byte;
0000946E 41 0A R5 = R5 + 1
0000946F 45 4A CMP R5,5
00009470 4C 4E JNE Chip_SectorErase
00009471 7C 95 R2=R4 LSR 4;
00009472 0C B3 0F 00 R1=R4 & 0x000F
00009474 59 93 R1=R1 LSL 4;
00009475 59 93 R1=R1 LSL 4;
00009476 59 93 R1=R1 LSL 4;
00009477 70 96 R3= 0x0030;
00009478 40 F0 BF 94 call Write_ST39VF040_One_Byte;
// CALL Delay100uS //delay 100us
0000947A 88 98 POP bp FROM [SP]
0000947B 90 9A RETF
//......................................................................
_ERASE_ST39VF040:
0000947C 88 DA PUSH bp TO [SP]
0000947D 40 9A R5 = 0x0000
Chip_MassErase_L:
0000947E 0D 03 12 97 R1 = R5 + Software_chiperase_addr
00009480 0D 07 18 97 R3 = R5 + Software_chiperase_data
00009482 C1 92 R1 = [R1] //get LOW address
00009483 C3 96 R3 = [R3] //get data
00009484 40 94 R2 = 0x0000 //get HIGH address
00009485 40 F0 BF 94 call Write_ST39VF040_One_Byte;
00009487 41 0A R5 = R5 + 1
00009488 46 4A CMP R5,6
00009489 4C 4E JNE Chip_MassErase_L
0000948A 40 F0 3A 95 CALL Delay11ms //delay 10ms
0000948C 88 98 POP bp FROM [SP]
0000948D 90 9A RETF
//----------------------------------------------------------------------
ProtectDisable:
0000948E A8 DA PUSH R1,R5 TO [SP]
0000948F 40 9A R5 = 0x0000
Chip_Protect_L:
00009490 0D 03 0C 97 R1 = R5 + Software_bytewrite_addr
00009492 0D 07 0F 97 R3 = R5 + Software_bytewrite_data
00009494 C1 92 R1 = [R1] //get LOW address
00009495 C3 96 R3 = [R3] //get data
00009496 40 94 R2 = 0x0000 //get HIGH address
00009497 40 F0 BF 94 call Write_ST39VF040_One_Byte;
00009499 41 0A R5 = R5 + 1
0000949A 43 4A CMP R5,3
0000949B 4C 4E JNE Chip_Protect_L
0000949C A8 90 POP R1,R5 FROM [SP]
0000949D 90 9A RETF
//----------------------------------------------------------------------
_Write_ST39VF040_One_Word:
0000949E A8 DA PUSH R1,R5 TO [SP]
0000949F 00 9B R5 = SP
000094A0 08 92 R1 = [R5 + 8] //get AddrL
000094A1 09 94 R2 = [R5 + 9] //get AddrH
000094A2 0A 96 R3 = [R5 + 10] //get Data
000094A3 0A 98 R4 = [R5 + 10]
000094A4 1C D9 FD 01 [Write_Byte]=R4
000094A6 0C B7 FF 00 R3=R4&0x00FF;
000094A8 40 F0 8E 94 CALL ProtectDisable
000094AA 40 F0 BF 94 CALL Write_ST39VF040_One_Byte
000094AC 09 43 FF FF CMP R1,0xFFFF;
000094AE 03 4E JNE Inc_WriteAddr;
000094AF 40 92 r1=0;
000094B0 41 04 r2+=1;
000094B1 01 EE jmp WriteNextByte;
Inc_WriteAddr:
000094B2 41 02 r1+=1;
WriteNextByte:
000094B3 14 99 FD 01 R4=[Write_Byte]
000094B5 7C 97 R3=R4 LSR 4;
000094B6 7B 97 R3=R3 LSR 4;
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