dev_gt.c

思科路由器仿真器,用来仿7200系列得,可以在电脑上模拟路由器-Cisco router simulator, used to fake a 7200 series can be simulated

         break;
      case 0x020:    /* ras32_high */
         if (op_type == MTS_READ)
            *data = swap32(0x7F);
         break;
      case 0x400:    /* ras0_low */
         if (op_type == MTS_READ)
            *data = swap32(0x00);
         break;
      case 0x404:    /* ras0_high */
         if (op_type == MTS_READ)
            *data = swap32(0xFF);
         break;
      case 0x408:    /* ras1_low */
         if (op_type == MTS_READ)
            *data = swap32(0x7F);
         break;
      case 0x40c:    /* ras1_high */
         if (op_type == MTS_READ)
            *data = swap32(0x00);
         break;
      case 0x410:    /* ras2_low */
         if (op_type == MTS_READ)
            *data = swap32(0x00);
         break;
      case 0x414:    /* ras2_high */
         if (op_type == MTS_READ)
            *data = swap32(0xFF);
         break;
      case 0x418:    /* ras3_low */
         if (op_type == MTS_READ)
            *data = swap32(0x7F);
         break;
      case 0x41c:    /* ras3_high */
         if (op_type == MTS_READ)
            *data = swap32(0x00);
         break;
      case 0xc08:    /* pci0_cs10 */
         if (op_type == MTS_READ)
            *data = swap32(0xFFF);
         break;
      case 0xc0c:    /* pci0_cs32 */
         if (op_type == MTS_READ)
            *data = swap32(0xFFF);
         break;

      case 0xc00:    /* pci_cmd */
         if (op_type == MTS_READ)
            *data = swap32(0x00008001);
         break;

      /* ===== Interrupt Cause Register ===== */
      case 0xc18:
         if (op_type == MTS_READ) {
            *data = swap32(gt_data->int_cause_reg);
         } else {
            gt_data->int_cause_reg &= swap32(*data);
            gt_update_irq_status(gt_data);
         }
         break;

      /* ===== Interrupt Mask Register ===== */
      case 0xc1c:
         if (op_type == MTS_READ)
            *data = swap32(gt_data->int_mask_reg);
         else {
            gt_data->int_mask_reg = swap32(*data);
            gt_update_irq_status(gt_data);
         }
         break;

      /* ===== PCI Configuration ===== */
      case PCI_BUS_ADDR:    /* pci configuration address (0xcf8) */
         pci_dev_addr_handler(cpu,gt_data->bus[0],op_type,TRUE,data);
         break;

      case PCI_BUS_DATA:    /* pci data address (0xcfc) */
         pci_dev_data_handler(cpu,gt_data->bus[0],op_type,TRUE,data);
         break;

#if DEBUG_UNKNOWN
      default:
         if (op_type == MTS_READ) {
            cpu_log(cpu,"GT64010","read from addr 0x%x, pc=0x%llx\n",
                    offset,cpu->pc);
         } else {
            cpu_log(cpu,"GT64010","write to addr 0x%x, value=0x%llx, "
                    "pc=0x%llx\n",offset,*data,cpu->pc);
         }
#endif
   }

   return NULL;
}

/*
 * dev_gt64120_access()
 */
void *dev_gt64120_access(cpu_mips_t *cpu,struct vdevice *dev,m_uint32_t offset,
                         u_int op_size,u_int op_type,m_uint64_t *data)
{
   struct gt_data *gt_data = dev->priv_data;
   
   if (op_type == MTS_READ)
      *data = 0;

   if (gt_dma_access(cpu,dev,offset,op_size,op_type,data) != 0)
      return NULL;

   switch(offset) {
      case 0x008:    /* ras10_low */
         if (op_type == MTS_READ)
            *data = swap32(0x000);
         break;
      case 0x010:    /* ras10_high */
         if (op_type == MTS_READ)
            *data = swap32(0x7F);
         break;
      case 0x018:    /* ras32_low */
         if (op_type == MTS_READ)
            *data = swap32(0x100);
         break;
      case 0x020:    /* ras32_high */
         if (op_type == MTS_READ)
            *data = swap32(0x7F);
         break;
      case 0x400:    /* ras0_low */
         if (op_type == MTS_READ)
            *data = swap32(0x00);
         break;
      case 0x404:    /* ras0_high */
         if (op_type == MTS_READ)
            *data = swap32(0xFF);
         break;
      case 0x408:    /* ras1_low */
         if (op_type == MTS_READ)
            *data = swap32(0x7F);
         break;
      case 0x40c:    /* ras1_high */
         if (op_type == MTS_READ)
            *data = swap32(0x00);
         break;
      case 0x410:    /* ras2_low */
         if (op_type == MTS_READ)
            *data = swap32(0x00);
         break;
      case 0x414:    /* ras2_high */
         if (op_type == MTS_READ)
            *data = swap32(0xFF);
         break;
      case 0x418:    /* ras3_low */
         if (op_type == MTS_READ)
            *data = swap32(0x7F);
         break;
      case 0x41c:    /* ras3_high */
         if (op_type == MTS_READ)
            *data = swap32(0x00);
         break;
      case 0xc08:    /* pci0_cs10 */
         if (op_type == MTS_READ)
            *data = swap32(0xFFF);
         break;
      case 0xc0c:    /* pci0_cs32 */
         if (op_type == MTS_READ)
            *data = swap32(0xFFF);
         break;

      case 0xc00:    /* pci_cmd */
         if (op_type == MTS_READ)
            *data = swap32(0x00008001);
         break;

      /* ===== Interrupt Cause Register ===== */
      case 0xc18:
         if (op_type == MTS_READ)
            *data = swap32(gt_data->int_cause_reg);
         else {
            gt_data->int_cause_reg &= swap32(*data);
            gt_update_irq_status(gt_data);
         }
         break;

      /* ===== Interrupt Mask Register ===== */
      case 0xc1c:
         if (op_type == MTS_READ) {
            *data = swap32(gt_data->int_mask_reg);
         } else {
            gt_data->int_mask_reg = swap32(*data);
            gt_update_irq_status(gt_data);
         }
         break;

      /* ===== PCI Bus 1 ===== */
      case 0xcf0:
         pci_dev_addr_handler(cpu,gt_data->bus[1],op_type,TRUE,data);
         break;

      case 0xcf4:
         pci_dev_data_handler(cpu,gt_data->bus[1],op_type,TRUE,data);
         break;
         
      /* ===== PCI Bus 0 ===== */
      case PCI_BUS_ADDR:    /* pci configuration address (0xcf8) */
         pci_dev_addr_handler(cpu,gt_data->bus[0],op_type,TRUE,data);
         break;

      case PCI_BUS_DATA:    /* pci data address (0xcfc) */
         pci_dev_data_handler(cpu,gt_data->bus[0],op_type,TRUE,data);
         break;

#if DEBUG_UNKNOWN
      default:
         if (op_type == MTS_READ) {
            cpu_log(cpu,"GT64120","read from addr 0x%x, pc=0x%llx\n",
                    offset,cpu->pc);
         } else {
            cpu_log(cpu,"GT64120","write to addr 0x%x, value=0x%llx, "
                    "pc=0x%llx\n",offset,*data,cpu->pc);
         }
#endif
   }

   return NULL;
}

/* Update the Ethernet port interrupt status */
static void gt_eth_update_int_status(struct gt_data *d,struct eth_port *port)
{
   if (port->icr & GT_ICR_MASK)
      port->icr |= GT_ICR_INT_SUM;

   if (port->icr & port->imr & GT_ICR_MASK)
      vm_set_irq(d->vm,d->eth_irq);
}

/* Read a MII register */
static m_uint32_t gt_mii_read(struct gt_data *d)
{
   m_uint8_t port,reg;
   m_uint32_t res = 0;

   port = (d->smi_reg & GT_SMIR_PHYAD_MASK) >> GT_SMIR_PHYAD_SHIFT;
   reg  = (d->smi_reg & GT_SMIR_REGAD_MASK) >> GT_SMIR_REGAD_SHIFT;

#if DEBUG_MII
   GT_LOG(d,"MII: port 0x%4.4x, reg 0x%2.2x: reading.\n",port,reg);
#endif

   if ((port < GT_ETH_PORTS) && (reg < 32)) {
      res = d->mii_regs[port][reg];

      switch(reg) {
         case 0x00:
            res &= ~0x8200; /* clear reset bit and autoneg restart */
            break;
         case 0x01:
#if 0
            if (d->ports[port].nio && bcm5600_mii_port_status(d,port))
               d->mii_output = 0x782C;
            else
               d->mii_output = 0;
#endif
            res = 0x782c;
            break;
         case 0x02:
            res = 0x40;
            break;
         case 0x03:
            res = 0x61d4;
            break;
         case 0x04:
            res = 0x1E1;
            break;
         case 0x05:
            res = 0x41E1;
            break;
         default:
            res = 0;
      }
   }

   /* Mark the data as ready */
   res |= GT_SMIR_RVALID_FLAG;

   return(res);
}

/* Write a MII register */
static void gt_mii_write(struct gt_data *d)
{
   m_uint8_t port,reg;
   m_uint16_t isolation;

   port = (d->smi_reg & GT_SMIR_PHYAD_MASK) >> GT_SMIR_PHYAD_SHIFT;
   reg  = (d->smi_reg & GT_SMIR_REGAD_MASK) >> GT_SMIR_REGAD_SHIFT;

   if ((port < GT_ETH_PORTS) && (reg < 32))
   {
#if DEBUG_MII
      GT_LOG(d,"MII: port 0x%4.4x, reg 0x%2.2x: writing 0x%4.4x\n",
             port,reg,d->smi_reg & GT_SMIR_DATA_MASK);
#endif

      /* Check if PHY isolation status is changing */
      if (reg == 0) {
         isolation = (d->smi_reg ^ d->mii_regs[port][reg]) & 0x400;

         if (isolation) {
#if DEBUG_MII
            GT_LOG(d,"MII: port 0x%4.4x: generating IRQ\n",port);
#endif
            d->eth_ports[port].icr |= GT_ICR_MII_STC;
            gt_eth_update_int_status(d,&d->eth_ports[port]);
         }
      }

      d->mii_regs[port][reg] = d->smi_reg & GT_SMIR_DATA_MASK;
   }
}

/* Handle registers of Ethernet ports */
static int gt_eth_access(cpu_mips_t *cpu,struct vdevice *dev,
                         m_uint32_t offset,u_int op_size,u_int op_type,
                         m_uint64_t *data)
{
   struct gt_data *d = dev->priv_data;
   struct eth_port *port;
   u_int port_id = 0;
   u_int queue;

   if ((offset < 0x80000) || (offset >= 0x90000))
      return(FALSE);

   if (op_type == MTS_WRITE)
      *data = swap32(*data);

   /* Detemine the Ethernet port */
   if ((offset >= 0x84800) && (offset < 0x88800))
      port_id = 0;

   if ((offset >= 0x88800) && (offset < 0x8c800))
      port_id = 1;

   port = &d->eth_ports[port_id];   

   switch(offset) {
      /* SMI register */
      case 0x80810:
         if (op_type == MTS_WRITE) {
            d->smi_reg = *data;

            if (!(d->smi_reg & GT_SMIR_OPCODE_READ))
               gt_mii_write(d);
         } else {
            *data = 0;

            if (d->smi_reg & GT_SMIR_OPCODE_READ)
               *data = gt_mii_read(d);
         }
         break;

      /* ICR: Interrupt Cause Register */
      case 0x84850:
      case 0x88850:
         if (op_type == MTS_READ)
            *data = port->icr;
         else
            port->icr &= *data;
         break;

      /* IMR: Interrupt Mask Register */
      case 0x84858:
      case 0x88858:
         if (op_type == MTS_READ)
            *data = port->imr;
         else
            port->imr = *data;
         break;

      /* PCR: Port Configuration Register */
      case 0x84800:
      case 0x88800:
         if (op_type == MTS_READ)
            *data = port->pcr;
         else
            port->pcr = *data;
         break;

      /* PCXR: Port Configuration Extend Register */
      case 0x84808:
      case 0x88808:
         if (op_type == MTS_READ) {
            *data = port->pcxr;
            *data |= GT_PCXR_SPEED;
         } else
            port->pcxr = *data;
         break;
         
      /* PCMR: Port Command Register */
      case 0x84810:
      case 0x88810:
         if (op_type == MTS_READ)
            *data = port->pcmr;
         else
            port->pcmr = *data;
         break;

      /* Port Status Register */
      case 0x84818:
      case 0x88818:
         if (op_type == MTS_READ)
            *data = 0x0F;
         break;

      /* First RX descriptor */
      case 0x84880:
      case 0x88880:
      case 0x84884:
      case 0x88884:
      case 0x84888:
      case 0x88888:
      case 0x8488C:
      case 0x8888C:
         queue = (offset >> 2) & 0x03;
         if (op_type == MTS_READ)
            *data = port->rx_start[queue];
         else
            port->rx_start[queue] = *data;
         break;

      /* Current RX descriptor */
      case 0x848A0:
      case 0x888A0:
      case 0x848A4:
      case 0x888A4:
      case 0x848A8:
      case 0x888A8:
      case 0x848AC:
      case 0x888AC:
         queue = (offset >> 2) & 0x03;
         if (op_type == MTS_READ)
            *data = port->rx_current[queue];
         else
            port->rx_current[queue] = *data;
         break;

      /* Current TX descriptor */
      case 0x848E0:
      case 0x888E0:
      case 0x848E4:
      case 0x888E4:
         queue = (offset >> 2) & 0x01;
         if (op_type == MTS_READ)
            *data = port->tx_current[queue];
         else
            port->tx_current[queue] = *data;
         break;

      /* Hash Table Pointer */
      case 0x84828:
      case 0x88828:
         if (op_type == MTS_READ)
            *data = port->ht_addr;
         else
            port->ht_addr = *data;
         break;

      /* SDCR: SDMA Configuration Register */
      case 0x84840:
      case 0x88840:
         if (op_type == MTS_READ)
            *data = port->sdcr;
         else
            port->sdcr = *data;
         break;

      /* SDCMR: SDMA Command Register */
      case 0x84848:
      case 0x88848:
         if (op_type == MTS_WRITE) {
            /* Start RX DMA */
            if (*data & GT_SDCMR_ERD) {
               port->sdcmr |= GT_SDCMR_ERD;
               port->sdcmr &= ~GT_SDCMR_AR;