dev_c7200_iofpga.c

思科路由器仿真器,用来仿7200系列得,可以在电脑上模拟路由器-Cisco router simulator, used to fake a 7200 series can be simulated

      case 0x294:
         /* 
          * Unknown, seen in 12.4(6)T, and seems to be read at each 
          * network interrupt.
          */
         if (op_type == MTS_READ)
            *data = 0x0;
         break;

      /* NPE-G1 test - unknown (value written: 0x01) */
      case 0x338:
         break;

      /* NPE-G1 test - has influence on slot 0 / flash / pcmcia ... */
      case 0x390:
         if (op_type == MTS_READ)
            *data = 0x0FFF0000; //0xFFFF0000;
         break;

      /* I/O control register */
      case 0x204:
         if (op_type == MTS_WRITE) {
#if DEBUG_IO_CTL
            vm_log(vm,"IO_FPGA","setting value 0x%llx in io_ctrl_reg\n",*data);
#endif
            d->io_ctrl_reg = *data;
         }
         else {
            *data = d->io_ctrl_reg;
            *data |= NVRAM_PACKED;              /* Packed NVRAM */
         }
         break;

      /* CPU/Midplane EEPROMs */
      case 0x21c:
         if (op_type == MTS_WRITE)
            nmc93c46_write(&d->router->sys_eeprom_g1,(u_int)(*data));
         else
            *data = nmc93c46_read(&d->router->sys_eeprom_g1);
         break;

      /* PEM (NPE-B) EEPROM */
      case 0x388:
          if (op_type == MTS_WRITE)
            nmc93c46_write(&d->router->sys_eeprom_g2,(u_int)(*data));
         else
            *data = nmc93c46_read(&d->router->sys_eeprom_g2);
         break;

      /* Watchdog */
      case 0x234:
         break;

      /* 
       * FPGA release/presence ? Flash SIMM size:
       *   0x0001: 2048K  Flash (2 banks)
       *   0x0504: 8192K  Flash (2 banks)
       *   0x0704: 16384K Flash (2 banks)
       *   0x0904: 32768K Flash (2 banks)
       *   0x0B04: 65536K Flash (2 banks)
       *   0x2001: 1024K  Flash (1 bank)
       *   0x2504: 4096K  Flash (1 bank)
       *   0x2704: 8192K  Flash (1 bank)
       *   0x2904: 16384K Flash (1 bank)
       *   0x2B04: 32768K Flash (1 bank)
       *
       *   Number of Flash SIMM banks + size.
       *   Touching some lower bits causes problems with environmental monitor.
       *
       * It is displayed by command "sh bootflash: chips"
       */
      case 0x23c:
         if (op_type == MTS_READ)
            *data = 0x2704;
         break;

      /* LEDs */
      case 0x244:
#if DEBUG_LED
         vm_log(vm,"IO_FPGA","LED register is now 0x%x (0x%x)\n",
                *data,(~*data) & 0x0F);
#endif
         break;

      /* ==== DUART SCN2681 (console/aux) ==== */
      case 0x404:   /* Mode Register A (MRA) */
         break;

      case 0x40c:   /* Status Register A (SRA) */
         if (op_type == MTS_READ) {
            odata = 0;

            if (vtty_is_char_avail(vm->vtty_con))
               odata |= DUART_RX_READY;

            odata |= DUART_TX_READY;
         
            vm_clear_irq(vm,C7200_DUART_IRQ);
            *data = odata;
         }
         break;

      case 0x414:   /* Command Register A (CRA) */
         /* Disable TX = High */
         if ((op_type == MTS_WRITE) && (*data & 0x8)) {
            vm->vtty_con->managed_flush = TRUE;          
            vtty_flush(vm->vtty_con);
         }
         break;

      case 0x41c:   /* RX/TX Holding Register A (RHRA/THRA) */
         if (op_type == MTS_WRITE) {
            vtty_put_char(vm->vtty_con,(char)*data);
            d->duart_isr &= ~DUART_TXRDYA;
         } else {
            *data = vtty_get_char(vm->vtty_con);
            d->duart_isr &= ~DUART_RXRDYA;
         }
         break;

      case 0x424:   /* WRITE: Aux Control Register (ACR) */
         break;

      case 0x42c:   /* Interrupt Status/Mask Register (ISR/IMR) */
         if (op_type == MTS_WRITE) {
            d->duart_imr = *data;
         } else
            *data = d->duart_isr;
         break;

      case 0x434:   /* Counter/Timer Upper Value (CTU) */
      case 0x43c:   /* Counter/Timer Lower Value (CTL) */
      case 0x444:   /* Mode Register B (MRB) */
         break;

      case 0x44c:   /* Status Register B (SRB) */
         if (op_type == MTS_READ) {
            odata = 0;

            if (vtty_is_char_avail(vm->vtty_aux))
               odata |= DUART_RX_READY;

            odata |= DUART_TX_READY;
         
            //vm_clear_irq(vm,C7200_DUART_IRQ);
            *data = odata;
         }
         break;

      case 0x454:   /* Command Register B (CRB) */
         /* Disable TX = High */
         if ((op_type == MTS_WRITE) && (*data & 0x8)) {
            vm->vtty_aux->managed_flush = TRUE;
            vtty_flush(vm->vtty_aux);
         }
         break;

      case 0x45c:   /* RX/TX Holding Register B (RHRB/THRB) */
         if (op_type == MTS_WRITE) {
            vtty_put_char(vm->vtty_aux,(char)*data);
            d->duart_isr &= ~DUART_TXRDYA;
         } else {
            *data = vtty_get_char(vm->vtty_aux);
            d->duart_isr &= ~DUART_RXRDYB;
         }
         break;

      case 0x46c:   /* WRITE: Output Port Configuration Register (OPCR) */
      case 0x474:   /* READ: Start Counter Command; */
                    /* WRITE: Set Output Port Bits Command */
      case 0x47c:   /* WRITE: Reset Output Port Bits Command */
         break;

      /* ==== DS 1620 (temp sensors) ==== */
      case 0x20c:   /* Temperature Control */
         if (op_type == MTS_WRITE)
            temp_write_ctrl(d,*data);
         break;

      case 0x214:   /* Temperature data write */
         if (op_type == MTS_WRITE) {
            temp_write_data(d,*data);
            d->mux = *data;
         }
         break;

      case 0x22c:   /* Temperature data read */
         if (op_type == MTS_READ)
            *data = temp_read_data(d);
         break;

      /* 
       * NPE-G1 - Voltages + Power Supplies.
       * I don't understand exactly how it works, it seems that the low
       * part must be equal to the high part to have the better values.
       */
      case 0x254:
#if DEBUG_ENVM
         vm_log(vm,"ENVM","access to envm a/d converter - mux = %u\n",d->mux);
#endif
         if (op_type == MTS_READ)
            *data = 0xFFFFFFFF;
         break;

      case 0x257:   /* ENVM A/D Converter */
#if DEBUG_ENVM
         vm_log(vm,"ENVM","access to envm a/d converter - mux = %u\n",d->mux);
#endif
         if (op_type == MTS_READ) {
            switch(d->mux) {
               case C7200_MUX_PS0:
                  *data = C7200_A2D_PS0;
                  break;

               case C7200_MUX_PS1:
                  *data = C7200_A2D_PS1;
                  break;

               case C7200_MUX_P3V:
                  *data = C7200_A2D_P3V;
                  break;

               case C7200_MUX_P12V:
                  *data = C7200_A2D_P12V;
                  break;

               case C7200_MUX_P5V:
                  *data = C7200_A2D_P5V;
                  break;

               case C7200_MUX_N12V:
                  *data = C7200_A2D_N12V;
                  break;
                  
               default:
                  *data = 0;
            }

            *data = *data / C7200_A2D_SAMPLES;
         }
         break;

#if DEBUG_UNKNOWN
      default:
         if (op_type == MTS_READ) {
            cpu_log(cpu,"IO_FPGA","read from addr 0x%x, pc=0x%llx (size=%u)\n",
                    offset,cpu->pc,op_size);
         } else {
            cpu_log(cpu,"IO_FPGA","write to addr 0x%x, value=0x%llx, "
                    "pc=0x%llx (size=%u)\n",offset,*data,cpu->pc,op_size);
         }
#endif
   }

   IOFPGA_UNLOCK(d);
   return NULL;
}

/* Initialize EEPROM groups */
void c7200_init_eeprom_groups(c7200_t *router)
{
   router->sys_eeprom_g1 = eeprom_cpu_midplane;
   router->sys_eeprom_g2 = eeprom_pem_npeb;

   router->sys_eeprom_g1.eeprom[0] = &router->cpu_eeprom;
   router->sys_eeprom_g1.eeprom[1] = &router->mp_eeprom;

   router->sys_eeprom_g2.eeprom[0] = &router->pem_eeprom;
}

/* Shutdown the IO FPGA device */
void dev_c7200_iofpga_shutdown(vm_instance_t *vm,struct iofpga_data *d)
{
   if (d != NULL) {
      IOFPGA_LOCK(d);
      vm->vtty_con->read_notifier = NULL;
      vm->vtty_aux->read_notifier = NULL;
      IOFPGA_UNLOCK(d);

      /* Remove the dummy IRQ periodic task */
      ptask_remove(d->duart_irq_tid);

      /* Remove the device */
      dev_remove(vm,&d->dev);

      /* Free the structure itself */
      free(d);
   }
}

/*
 * dev_c7200_iofpga_init()
 */
int dev_c7200_iofpga_init(c7200_t *router,m_uint64_t paddr,m_uint32_t len)
{
   vm_instance_t *vm = router->vm;
   struct iofpga_data *d;
   u_int i;

   /* Allocate private data structure */
   if (!(d = malloc(sizeof(*d)))) {
      fprintf(stderr,"IO_FPGA: out of memory\n");
      return(-1);
   }

   memset(d,0,sizeof(*d));

   pthread_mutex_init(&d->lock,NULL);
   d->router = router;

   for(i=0;i<C7200_TEMP_SENSORS;i++) {
      d->temp_cfg_reg[i] = DS1620_CONFIG_STATUS_CPU;
      d->temp_deg_reg[i] = C7200_DEFAULT_TEMP * 2;
   }

   vm_object_init(&d->vm_obj);
   d->vm_obj.name = "io_fpga";
   d->vm_obj.data = d;
   d->vm_obj.shutdown = (vm_shutdown_t)dev_c7200_iofpga_shutdown;

   /* Set device properties */
   dev_init(&d->dev);
   d->dev.name      = "io_fpga";
   d->dev.phys_addr = paddr;
   d->dev.phys_len  = len;
   d->dev.handler   = dev_c7200_iofpga_access;
   d->dev.priv_data = d;

   /* Set console and AUX port notifying functions */
   vm->vtty_con->priv_data = d;
   vm->vtty_aux->priv_data = d;
   vm->vtty_con->read_notifier = tty_con_input;
   vm->vtty_aux->read_notifier = tty_aux_input;

   /* Trigger periodically a dummy IRQ to flush buffers */
   d->duart_irq_tid = ptask_add((ptask_callback)tty_trigger_dummy_irq,d,NULL);

   /* Map this device to the VM */
   vm_bind_device(vm,&d->dev);
   vm_object_add(vm,&d->vm_obj);
   return(0);
}