📄 mips64_jit.c
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patch = &ipt->patches[i]; jit_dst = insn_block_get_jit_ptr(block,patch->mips_pc); if (jit_dst) {#if DEBUG_BLOCK_PATCH printf("Block 0x%8.8llx: applying patch " "[JIT:%p->mips:0x%8.8llx=JIT:%p]\n", block->start_pc,patch->jit_insn,patch->mips_pc,jit_dst);#endif insn_block_set_patch(patch->jit_insn,jit_dst); } } return(0);}/* Free the patch table */static void insn_block_free_patches(insn_block_t *block){ struct insn_patch_table *p,*next; for(p=block->patch_table;p;p=next) { next = p->next; free(p); } block->patch_table = NULL;}/* Adjust the JIT buffer if its size is not sufficient */int insn_block_adjust_jit_buffer(cpu_mips_t *cpu,insn_block_t *block){ insn_exec_page_t *new_buffer; if ((block->jit_ptr - block->jit_buffer->ptr) <= (MIPS_JIT_BUFSIZE - 512)) return(0);#if DEBUG_BLOCK_CHUNK printf("Block 0x%llx: adjusting JIT buffer...\n",block->start_pc);#endif if (block->jit_chunk_pos >= INSN_MAX_CHUNKS) { fprintf(stderr,"Block 0x%llx: too many JIT chunks.\n",block->start_pc); return(-1); } if (!(new_buffer = exec_page_alloc(cpu))) return(-1); /* record the new exec page */ block->jit_chunks[block->jit_chunk_pos++] = block->jit_buffer; block->jit_buffer = new_buffer; /* jump to the new exec page (link) */ insn_block_set_jump(block->jit_ptr,new_buffer->ptr); block->jit_ptr = new_buffer->ptr; return(0);}/* Allocate an instruction block */static inline insn_block_t *insn_block_alloc(cpu_mips_t *cpu){ insn_block_t *p; if (cpu->insn_block_free_list) { p = cpu->insn_block_free_list; cpu->insn_block_free_list = p->next; } else { if (!(p = malloc(sizeof(*p)))) return NULL; } memset(p,0,sizeof(*p)); return p;}/* Free an instruction block */void insn_block_free(cpu_mips_t *cpu,insn_block_t *block,int list_removal){ int i; if (block) { if (list_removal) { /* Remove the block from the linked list */ if (block->next) block->next->prev = block->prev; else cpu->insn_block_last = block->prev; if (block->prev) block->prev->next = block->next; else cpu->insn_block_list = block->next; } /* Free the patch tables */ insn_block_free_patches(block); /* Free code pages */ for(i=0;i<INSN_MAX_CHUNKS;i++) exec_page_free(cpu,block->jit_chunks[i]); /* Free the current JIT buffer */ exec_page_free(cpu,block->jit_buffer); /* Free the MIPS-to-native code mapping */ free(block->jit_insn_ptr); /* Make the block return to the free list */ block->next = cpu->insn_block_free_list; cpu->insn_block_free_list = block; }}/* Create an instruction block */static insn_block_t *insn_block_create(cpu_mips_t *cpu,m_uint64_t vaddr){ insn_block_t *block = NULL; if (!(block = insn_block_alloc(cpu))) goto err_block_alloc; block->start_pc = vaddr; /* Allocate the first JIT buffer */ if (!(block->jit_buffer = exec_page_alloc(cpu))) goto err_jit_alloc; block->jit_ptr = block->jit_buffer->ptr; block->mips_code = cpu->mem_op_lookup(cpu,block->start_pc); if (!block->mips_code) { fprintf(stderr,"%% No memory map for code execution at 0x%llx\n", block->start_pc); goto err_lookup; }#if DEBUG_BLOCK_TIMESTAMP block->tm_first_use = block->tm_last_use = jit_jiffies;#endif return block; err_lookup: err_jit_alloc: insn_block_free(cpu,block,FALSE); err_block_alloc: fprintf(stderr,"%% Unable to create instruction block for vaddr=0x%llx\n", vaddr); return NULL;}/* Compile a MIPS instruction page */static inline insn_block_t *insn_page_compile(cpu_mips_t *cpu,m_uint64_t vaddr){ m_uint64_t page_addr; insn_block_t *block; struct insn_tag *tag; size_t len; page_addr = vaddr & ~(m_uint64_t)MIPS_MIN_PAGE_IMASK; if (unlikely(!(block = insn_block_create(cpu,page_addr)))) { fprintf(stderr,"insn_page_compile: unable to create JIT block.\n"); return NULL; } /* Allocate the array used to convert MIPS code ptr to native code ptr */ len = MIPS_MIN_PAGE_SIZE / sizeof(mips_insn_t); if (!(block->jit_insn_ptr = calloc(len,sizeof(u_char *)))) { fprintf(stderr,"insn_page_compile: unable to create JIT mappings.\n"); goto error; } /* Emit native code for each instruction */ block->mips_trans_pos = 0; while(block->mips_trans_pos < (MIPS_MIN_PAGE_SIZE/sizeof(mips_insn_t))) { if (unlikely(!(tag = insn_fetch_and_emit(cpu,block,0)))) { fprintf(stderr,"insn_page_compile: unable to fetch instruction.\n"); goto error; }#if DEBUG_BLOCK_COMPILE printf("Page 0x%8.8llx: emitted tag 0x%8.8x/0x%8.8x\n", block->start_pc,tag->mask,tag->value);#endif insn_block_adjust_jit_buffer(cpu,block); } insn_block_add_end(block); insn_block_apply_patches(cpu,block); insn_block_free_patches(block); /* Add the block to the linked list */ block->next = cpu->insn_block_list; block->prev = NULL; if (cpu->insn_block_list) cpu->insn_block_list->prev = block; else cpu->insn_block_last = block; cpu->insn_block_list = block; cpu->compiled_pages++; return block; error: insn_block_free(cpu,block,FALSE); return NULL;}/* Run a compiled MIPS instruction block */static forced_inline void insn_block_run(cpu_mips_t *cpu,insn_block_t *block){#if DEBUG_SYM_TREE struct symbol *sym = NULL; int mark = FALSE;#endif if (unlikely(cpu->pc & 0x03)) { fprintf(stderr,"insn_block_run: Invalid PC 0x%llx.\n",cpu->pc); mips64_dump_regs(cpu); tlb_dump(cpu); cpu_stop(cpu); return; }#if DEBUG_SYM_TREE if (cpu->sym_trace && cpu->sym_tree) { if ((sym = mips64_sym_lookup(cpu,cpu->pc)) != NULL) { cpu_log(cpu,"insn_block_run(start)", "%s (PC=0x%llx) RA = 0x%llx\na0=0x%llx, " "a1=0x%llx, a2=0x%llx, a3=0x%llx\n", sym->name, cpu->pc, cpu->gpr[MIPS_GPR_RA], cpu->gpr[MIPS_GPR_A0], cpu->gpr[MIPS_GPR_A1], cpu->gpr[MIPS_GPR_A2], cpu->gpr[MIPS_GPR_A3]); mark = TRUE; } }#endif /* Execute JIT compiled code */ insn_block_exec_jit_code(cpu,block);#if DEBUG_SYM_TREE if (mark) { cpu_log(cpu,"insn_block_run(end)","%s, v0 = 0x%llx\n", sym->name,cpu->gpr[MIPS_GPR_V0]); }#endif}/* Check if the specified address belongs to the specified block */int insn_block_local_addr(insn_block_t *block,m_uint64_t vaddr, u_char **jit_addr){ if ((vaddr >= block->start_pc) && ((vaddr - block->start_pc) < MIPS_MIN_PAGE_SIZE)) { *jit_addr = insn_block_get_jit_ptr(block,vaddr); return(1); } return(0);}/* Check if PC register matches the compiled block virtual address */static forced_inline int insn_block_match(cpu_mips_t *cpu,insn_block_t *block){ m_uint64_t vpage; vpage = cpu->pc & ~(m_uint64_t)MIPS_MIN_PAGE_IMASK; return(block->start_pc == vpage);}/* Execute a compiled MIPS code */void *insn_block_execute(cpu_mips_t *cpu){ pthread_t timer_irq_thread; insn_block_t *block; m_uint32_t phys_page; int timer_irq_check = 0; if (pthread_create(&timer_irq_thread,NULL, (void *)mips64_timer_irq_run,cpu)) { fprintf(stderr, "VM '%s': unable to create Timer IRQ thread for CPU%u.\n", cpu->vm->name,cpu->id); cpu_stop(cpu); return NULL; } cpu->cpu_thread_running = TRUE; start_cpu: cpu->idle_count = 0; for(;;) { if (unlikely(cpu->state != MIPS_CPU_RUNNING)) break; /* Handle virtual idle loop */ if (unlikely(cpu->pc == cpu->idle_pc)) { if (++cpu->idle_count == cpu->idle_max) { mips64_idle_loop(cpu); cpu->idle_count = 0; } } /* Handle the virtual CPU clock */ if (++timer_irq_check == cpu->timer_irq_check_itv) { timer_irq_check = 0; if (cpu->timer_irq_pending && !cpu->irq_disable) { mips64_trigger_timer_irq(cpu); mips64_trigger_irq(cpu); cpu->timer_irq_pending--; } } /* Get the physical page address corresponding to PC register */ if (unlikely(cpu->translate(cpu,cpu->pc,&phys_page))) { fprintf(stderr,"VM '%s': no physical page for CPU%u PC=0x%llx\n", cpu->vm->name,cpu->id,cpu->pc); cpu_stop(cpu); break; } block = cpu->exec_phys_map[phys_page]; /* No block found, compile the page */ if (unlikely(!block) || unlikely(!insn_block_match(cpu,block))) { if (block != NULL) { insn_block_free(cpu,block,TRUE); cpu->exec_phys_map[phys_page] = NULL; } block = insn_page_compile(cpu,cpu->pc); if (unlikely(!block)) { fprintf(stderr, "VM '%s': unable to compile block for CPU%u PC=0x%llx\n", cpu->vm->name,cpu->id,cpu->pc); cpu_stop(cpu); break; } block->phys_page = phys_page; cpu->exec_phys_map[phys_page] = block; }#if DEBUG_BLOCK_TIMESTAMP block->tm_last_use = jit_jiffies++;#endif block->acc_count++; insn_block_run(cpu,block); } if (!cpu->pc) { cpu_stop(cpu); cpu_log(cpu,"JIT","PC=0, halting CPU.\n"); } /* Check regularly if the CPU has been restarted */ while(cpu->cpu_thread_running) { cpu->seq_state++; switch(cpu->state) { case MIPS_CPU_RUNNING: cpu->state = MIPS_CPU_RUNNING; goto start_cpu; case MIPS_CPU_HALTED: cpu->cpu_thread_running = FALSE; pthread_join(timer_irq_thread,NULL); break; } /* CPU is paused */ usleep(200000); } return NULL;}
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