📄 blackfin_memory_map.h
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/*****************************************************************************
** **
** Name: LDF for Blackfin processors **
** **
******************************************************************************
(C) Copyright 2006-2007 - Analog Devices, Inc. All rights reserved.
The known memory spaces are as follows:
0xFFE00000 - 0xFFFFFFFF Core MMR registers (2MB)
0xFFC00000 - 0xFFDFFFFF System MMR registers (2MB)
0xFFB01000 - 0xFFBFFFFF Reserved
0xFFB00000 - 0xFFB00FFF Scratch SRAM (4K)
0xFFA24000 - 0xFFAFFFFF Reserved
0xFFA14000 - 0xFFA23FFF L1 Instruction ROM (64K)
0xFFA10000 - 0xFFA13FFF L1 Code SRAM / cache (16K)
0xFFA00000 - 0xFFA0FFFF L1 Code SRAM (64K)
0xFF908000 - 0xFF9FFFFF Reserved
0xFF904000 - 0xFF907FFF L1 Data Bank B SRAM / cache (16K)
0xFF900000 - 0xFF903FFF L1 Data Bank B SRAM (16K)
0xFF808000 - 0xFF8FFFFF Reserved
0xFF804000 - 0xFF807FFF L1 Data Bank A SRAM / cache (16K)
0xFF800000 - 0xFF803FFF L1 Data Bank A SRAM (16K)
0xFEB00000 - 0xFEB1FFFF L2 SRAM (128K)
0xEF000000 - 0xFF7FFFFF Reserved
0x20400000 - 0xEEFFFFFF Reserved
0x20300000 - 0x203FFFFF ASYNC MEMORY BANK 3 (1MB)
0x20200000 - 0x202FFFFF ASYNC MEMORY BANK 2 (1MB)
0x20100000 - 0x201FFFFF ASYNC MEMORY BANK 1 (1MB)
0x20000000 - 0x200FFFFF ASYNC MEMORY BANK 0 (1MB)
0x00000000 - 0x07FFFFFF SDRAM MEMORY (16MB - 128MB)
L1 Instruction Memory Bank C Subbanks: 0xFFA10000 - 0xFFA13FFF (16k)
0xFFA13000 - 0xFFA13FFF Instruction SRAM / cache Subbank 3 (4k)
0xFFA12000 - 0xFFA12FFF Instruction SRAM / cache Subbank 2 (4k)
0xFFA11000 - 0xFFA11FFF Instruction SRAM / cache Subbank 1 (4k)
0xFFA10000 - 0xFFA10FFF Instruction SRAM / cache Subbank 0 (4k)
L1 Instruction Memory Bank B Subbanks: 0xFFA08000 - 0xFFA0BFFF (16k) / 0xFFA08000 - 0xFFA0FFFF (32k)
0xFFA0F000 - 0xFFA0FFFF Instruction SRAM Bank C Subbank 7 (4k) (ADSP-BF533 only)
0xFFA0E000 - 0xFFA0EFFF Instruction SRAM Bank C Subbank 6 (4k) (ADSP-BF533 only)
0xFFA0D000 - 0xFFA0DFFF Instruction SRAM Bank C Subbank 5 (4k) (ADSP-BF533 only)
0xFFA0C000 - 0xFFA0CFFF Instruction SRAM Bank C Subbank 4 (4k) (ADSP-BF533 only)
0xFFA0B000 - 0xFFA0BFFF Instruction SRAM Bank B Subbank 3 (4k)
0xFFA0A000 - 0xFFA0AFFF Instruction SRAM Bank B Subbank 2 (4k)
0xFFA09000 - 0xFFA09FFF Instruction SRAM Bank B Subbank 1 (4k)
0xFFA08000 - 0xFFA08FFF Instruction SRAM Bank B Subbank 0 (4k)
L1 Instruction Memory Bank A Subbanks: 0xFFA00000 - 0xFFA07FFF (32k)
0xFFA07000 - 0xFFA07FFF Instruction SRAM Bank A Subbank 7 (4k)
0xFFA06000 - 0xFFA06FFF Instruction SRAM Bank A Subbank 6 (4k)
0xFFA05000 - 0xFFA05FFF Instruction SRAM Bank A Subbank 5 (4k)
0xFFA04000 - 0xFFA04FFF Instruction SRAM Bank A Subbank 4 (4k)
0xFFA03000 - 0xFFA03FFF Instruction SRAM Bank A Subbank 3 (4k)
0xFFA02000 - 0xFFA02FFF Instruction SRAM Bank A Subbank 2 (4k)
0xFFA01000 - 0xFFA01FFF Instruction SRAM Bank A Subbank 1 (4k)
0xFFA00000 - 0xFFA00FFF Instruction SRAM Bank A Subbank 0 (4k)
L1 Data Memory Bank B Subbanks: 0xFF900000 - 0xFF903FFF (16k) / 0xFF900000 - 0xFF907FFF (32k)
0xFF907000 - 0xFF907FFF Data SRAM / cache Bank B Subbank 7 (4k)
0xFF906000 - 0xFF906FFF Data SRAM / cache Bank B Subbank 6 (4k)
0xFF905000 - 0xFF905FFF Data SRAM / cache Bank B Subbank 5 (4k)
0xFF904000 - 0xFF904FFF Data SRAM / cache Bank B Subbank 4 (4k) // SUB 4-7 can be used as cache
0xFF903000 - 0xFF903FFF Data SRAM Bank B Subbank 3 (4k)
0xFF902000 - 0xFF902FFF Data SRAM Bank B Subbank 2 (4k)
0xFF901000 - 0xFF901FFF Data SRAM Bank B Subbank 1 (4k)
0xFF900000 - 0xFF900FFF Data SRAM Bank B Subbank 0 (4k)
L1 Data Memory Bank A Subbanks: 0xFF800000 - 0xFF803FFF (16k) / 0xFF800000 - 0xFF807FFF (32k)
0xFF807000 - 0xFF807FFF Data SRAM / cache Bank A Subbank 7 (4k)
0xFF806000 - 0xFF806FFF Data SRAM / cache Bank A Subbank 6 (4k)
0xFF805000 - 0xFF805FFF Data SRAM / cache Bank A Subbank 5 (4k)
0xFF804000 - 0xFF804FFF Data SRAM / cache Bank A Subbank 4 (4k) // SUB 4-7 can be used as cache
0xFF803000 - 0xFF803FFF Data SRAM Bank A Subbank 3 (4k)
0xFF802000 - 0xFF802FFF Data SRAM Bank A Subbank 2 (4k)
0xFF801000 - 0xFF801FFF Data SRAM Bank A Subbank 1 (4k)
0xFF800000 - 0xFF800FFF Data SRAM Bank A Subbank 0 (4k)
L2 SRAM: 0xFEB00000 - 0xFEB1FFFF (128K). L2 SRAM Memory block is organized into eight banks. Can be used for both code and data.
0xFEB1C000 - 0xFEB1FFFF L2 SRAM (16k) (ADSP-BF549/8 only)
0xFEB18000 - 0xFEB1BFFF L2 SRAM (16k) (ADSP-BF549/8 only)
0xFEB14000 - 0xFEB17FFF L2 SRAM (16k) (ADSP-BF549/8 only)
0xFEB10000 - 0xFEB13FFF L2 SRAM (16k) (ADSP-BF549/8 only)
0xFEB0C000 - 0xFEB0FFFF L2 SRAM (16k) (ADSP-BF549/8 only)
0xFEB08000 - 0xFEB0BFFF L2 SRAM (16k) (ADSP-BF549/8 only)
0xFEB04000 - 0xFEB07FFF L2 SRAM (16k) (ADSP-BF549/8 only)
0xFEB00000 - 0xFEB03FFF L2 SRAM (16k) (ADSP-BF549/8 only)
SDRAM MEMORY (e.g. 64MB): (0x00000000 - 0x03FFFFFF)
0x03000000 - 0x03FFFFFF SDRAM MEMORY BANK 3 (16MB)
0x02000000 - 0x02FFFFFF SDRAM MEMORY BANK 2 (16MB)
0x01000000 - 0x01FFFFFF SDRAM MEMORY BANK 1 (16MB)
0x00000000 - 0x00FFFFFF SDRAM MEMORY BANK 0 (16MB)
Notes:
0xFF807FEF-0xFF807FFF
Required by boot-loader. Used as heap or cache below which is ok.
Cannot contain initialized data or code.
*****************************************************************************/
#define L1_BANK_LENGTH 0x4000 /* 16kB */
#define L1_SBANK_LENGTH 0x1000 /* 4kB */
#define CORE_MMR_LENGTH 0x00200000 /* System MMR Register 2MB */
#define CORE_MMR_END 0xFFFFFFFF
#define CORE_MMR_START 0xFFE00000
#define SYS_MMR_LENGTH 0x00200000 /* Core MMR Register 2MB */
#define SYS_MMR_END 0xFFDFFFFF
#define SYS_MMR_START 0xFFC00000
#define SCRATCH_LENGTH 0x00001000 /* Scratchpad SRAM 4kB */
#define SCRATCH_END 0xFFB00FFF
#define SCRATCH_START 0xFFB00000
#define INSTR_CACHE_LENGTH 0x4000 /* 16kB */
#define INSTR_CACHE_START 0xFFA10000
#define INSTR_CACHE_END 0xFFA13FFF
#define DATA_CACHE_LENGTH 0x4000 /* 16kB */
#define DATA_CACHE_A_LENGTH DATA_CACHE_LENGTH
#define DATA_CACHE_A_START 0xFF804000
#define DATA_CACHE_A_END 0xFF807FFF
#if !defined __ADSPBF531__
#define DATA_CACHE_B_LENGTH DATA_CACHE_LENGTH
#define DATA_CACHE_B_START 0xFF904000
#define DATA_CACHE_B_END 0xFF907FFF
#endif
#if defined (__ADSPBF531__) || defined (__ADSPBF532__)
#define INSTR_SRAM_START 0xFFA08000
#else
#define INSTR_SRAM_START 0xFFA00000
#endif
#if defined __ADSPBF531__
#define INSTR_SRAM_LENGTH 0x4000 /* 16kB */
#define INSTR_SRAM_END 0xFFA0BFFF
#define INSTR_SRAM_B_LENGTH 0x4000 /* 16kB */
#define INSTR_SRAM_B_END 0xFFA0BFFF
#define INSTR_SRAM_B_START 0xFFA08000
#endif
#if defined __ADSPBF532__
#if defined INSTR_CACHE_EN
#define INSTR_SRAM_LENGTH 0x8000 /* 32kB */
#define INSTR_SRAM_END 0xFFA0FFFF
#else
#define INSTR_SRAM_LENGTH 0xC000 /* 48kB */
#define INSTR_SRAM_END 0xFFA13FFF
#endif
#define INSTR_SRAM_C_LENGTH 0x4000 /* 16kB */
#define INSTR_SRAM_C_END 0xFFA0FFFF
#define INSTR_SRAM_C_START 0xFFA0C000
#define INSTR_SRAM_B_LENGTH 0x4000 /* 16kB */
#define INSTR_SRAM_B_END 0xFFA0BFFF
#define INSTR_SRAM_B_START INSTR_SRAM_START
#endif
#if defined (__ADSPBF533__) || defined (__ADSPBF538__) || defined (__ADSPBF539__)
#if defined INSTR_CACHE_EN
#define INSTR_SRAM_LENGTH 0x10000 /* 64kB */
#define INSTR_SRAM_END 0xFFA0FFFF
#else
#define INSTR_SRAM_LENGTH 0x14000 /* 80kB */
#define INSTR_SRAM_END 0xFFA13FFF
#endif
#define INSTR_SRAM_C_LENGTH 0x4000 /* 16kB */
#define INSTR_SRAM_C_END 0xFFA0FFFF
#define INSTR_SRAM_C_START 0xFFA0C000
#define INSTR_SRAM_B_LENGTH 0x4000 /* 16kB */
#define INSTR_SRAM_B_END 0xFFA0BFFF
#define INSTR_SRAM_B_START 0xFFA08000
#define INSTR_SRAM_A_LENGTH 0x8000 /* 32kB */
#define INSTR_SRAM_A_END 0xFFA07FFF
#define INSTR_SRAM_A_START INSTR_SRAM_START
#endif
#if defined (__ADSPBF527__) || defined (__ADSPBF534__) || defined (__ADSPBF536__) || defined (__ADSPBF537__) || defined (__ADSPBF54x__)
#define INSTR_SRAM_LENGTH 0xC000 /* 48kB */
#define INSTR_SRAM_END 0xFFA0BFFF
#define INSTR_SRAM_B_LENGTH 0x4000 /* 16kB */
#define INSTR_SRAM_B_END 0xFFA0BFFF
#define INSTR_SRAM_B_START 0xFFA08000
#define INSTR_SRAM_A_LENGTH 0x8000 /* 32kB */
#define INSTR_SRAM_A_END 0xFFA07FFF
#define INSTR_SRAM_A_START INSTR_SRAM_START
#endif
#if defined __ADSPBF54x__
#define INSTR_ROM_LENGTH 0x10000 /* Instr. ROM 64kB */
#define INSTR_ROM_END 0xFFA23FFF
#define INSTR_ROM_START 0xFFA14000
#endif
#if defined __ADSPBF531__
#if defined (DATA_CACHE_EN) && defined (DATA_CACHE_AB)
#else
#endif
#if defined DATA_CACHE_EN
#else
#define DATA_SRAM_A_LENGTH 0x4000 /* 16kB */
#define DATA_SRAM_A_END 0xFF807FFF
#define DATA_SRAM_A_START 0xFF804000
#endif
#endif
#if defined (__ADSPBF532__) || defined (__ADSPBF536__)
#if defined (DATA_CACHE_EN) && defined (DATA_CACHE_AB)
#else
#define DATA_SRAM_B_LENGTH 0x4000 /* 16kB */
#define DATA_SRAM_B_END 0xFF907FFF
#define DATA_SRAM_B_START 0xFF904000
#endif
#if defined DATA_CACHE_EN
#else
#define DATA_SRAM_A_LENGTH 0x4000 /* 16kB */
#define DATA_SRAM_A_END 0xFF807FFF
#define DATA_SRAM_A_START 0xFF804000
#endif
#endif
#if defined (__ADSPBF527__) || defined (__ADSPBF533__) || defined (__ADSPBF538__) || defined (__ADSPBF539__) || defined (__ADSPBF534__) || defined (__ADSPBF537__) || defined (__ADSPBF548__)
#if defined (DATA_CACHE_EN) && defined (DATA_CACHE_AB)
#define DATA_SRAM_B_LENGTH 0x4000 /* 16kB */
#define DATA_SRAM_B_END 0xFF903FFF
#define DATA_SRAM_B_START 0xFF900000
#else
#define DATA_SRAM_B_LENGTH 0x8000 /* 32kB */
#define DATA_SRAM_B_END 0xFF907FFF
#define DATA_SRAM_B_START 0xFF900000
#endif
#if defined DATA_CACHE_EN
#define DATA_SRAM_A_LENGTH 0x4000 /* 16kB */
#define DATA_SRAM_A_END 0xFF803FFF
#define DATA_SRAM_A_START 0xFF800000
#else
#define DATA_SRAM_A_LENGTH 0x8000 /* 32kB */
#define DATA_SRAM_A_END 0xFF807FFF
#define DATA_SRAM_A_START 0xFF800000
#endif
#endif
#if defined __ADSPBF54x__
#if !defined __ADSPBF542__
#define L2_SRAM_END 0xFEB1FFFF
#define L2_SRAM_START 0xFEB00000
#endif
#if defined __ADSPBF544__
#define L2_SRAM_LENGTH 0x10000 /* L2 SRAM 64kB */
#endif
#if defined (__ADSPBF547__) || defined (__ADSPBF548__) || defined (__ADSPBF549__)
#define L2_SRAM_LENGTH 0x20000 /* L2 SRAM 128kB */
#endif
#endif
#if defined SDRAM_SIZE
#define SDRAM_START 0x00000000
#define SDRAM_BANK0_START SDRAM_START
#if SDRAM_SIZE == 128
#define SDRAM_LENGTH 0x08000000
#define SDRAM_END 0x07FFFFFF
#define SDRAM_BANK_LENGTH 0x02000000
#define SDRAM_BANK3_START 0x06000000
#define SDRAM_BANK2_START 0x04000000
#define SDRAM_BANK1_START SDRAM_BANK_LENGTH
#endif
#if SDRAM_SIZE == 64
#define SDRAM_LENGTH 0x04000000
#define SDRAM_END 0x03FFFFFF
#define SDRAM_BANK_LENGTH 0x01000000
#define SDRAM_BANK3_START 0x03000000
#define SDRAM_BANK2_START 0x02000000
#define SDRAM_BANK1_START SDRAM_BANK_LENGTH
#endif
#if SDRAM_SIZE == 32
#define SDRAM_LENGTH 0x02000000
#define SDRAM_END 0x01FFFFFF
#define SDRAM_BANK_LENGTH 0x00800000
#define SDRAM_BANK3_START 0x01800000
#define SDRAM_BANK2_START 0x01000000
#define SDRAM_BANK1_START SDRAM_BANK_LENGTH
#endif
#if SDRAM_SIZE == 16
#define SDRAM_LENGTH 0x01000000
#define SDRAM_END 0x00FFFFFF
#define SDRAM_BANK_LENGTH 0x00400000
#define SDRAM_BANK3_START 0x00C00000
#define SDRAM_BANK2_START 0x00800000
#define SDRAM_BANK1_START SDRAM_BANK_LENGTH
#endif
#endif
/*****************************************************************************
EOF
******************************************************************************/
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