bfstartup.asm

ADI公司SHARC与BlackFin通过SPI协议相互通信的源代码

/*****************************************************************************
**                                                                          **
**      Name:   bfstartup                                                   **
**                                                                          **
******************************************************************************

(C) Copyright 2007 - Analog Devices, Inc.  All rights reserved.

File Name:      bfstartup.asm

Date Modified:  05/08/08    v1.0 ap-muc

History:        06/14/06    v0

Tested
Software:       VisualDSP++ 4.0 (Updated June 2006)
                VisualDSP++ 4.5 (Updated Nov. 2006)
                VisualDSP++ 4.5 (Updated Feb. 2007)
                VisualDSP++ 5.0
                VisualDSP++ 5.0.1.0 (Update 1)
                VisualDSP++ 5.0.2.0 (Update 2)

Tested
Hardware:       ADSP-BF527 EZ-KIT Lite Rev. 1.0 Silicon Rev. 0.0
                ADSP-BF533 EZ-KIT Lite Rev. 1.7 Silicon Rev. 0.4
                ADSP-BF533 EZ-KIT Lite Rev. 2.1 Silicon Rev. 0.5
                ADSP-BF537 EZ-KIT Lite Rev. 1.3 Silicon Rev. 0.2
                ADSP-BF538 EZ-KIT Lite Rev. 1.2 Silicon Rev. 0.3
                ADSP-BF548 EZ-KIT Lite Rev. 1.2 Silicon Rev. 0.0
                ADSP-BF548 EZ-KIT Lite Rev. 1.3 Silicon Rev. 0.0
                ADSP-BF548 EZ-KIT Lite Rev. 2.1 Silicon Rev. 0.1
                ADSP-BF561 EZ-KIT Lite Rev. 1.3 Silicon Rev. 0.3
                ADSP-BF561 EZ-KIT Lite Rev. 2.1 Silicon Rev. 0.5

Supported
Plattforms:     ADSP-BF527 EZ-KIT Lite
                ADSP-BF533 EZ-KIT Lite Rev 1.6 and below (modifications required, only 32MB SDRAM installed)
                ADSP-BF533 EZ-KIT Lite Rev 1.7 and above
                ADSP-BF537 EZ-KIT Lite
                ADSP-BF538 EZ-KIT Lite
                ADSP-BF548 EZ-KIT Lite
                ADSP-BF561 EZ-KIT Lite (Silicon Rev. 0.2 and beyond)

Connections:    ADDS-HPUSB-ICE

Settings:       Default

Purpose:        Generic Startup file for
                ADSP-BF527 EZ-KIT LITE
                ADSP-BF533 EZ-KIT LITE
                ADSP-BF537 EZ-KIT LITE
                ADSP-BF538 EZ-KIT LITE
                ADSP-BF548 EZ-KIT LITE
                ADSP-BF561 EZ-KIT LITE
                tests.

*****************************************************************************/


/****************************************************************************
 Include Section
*****************************************************************************/

#include "configurations.h"
#include <blackfin.h>

#include "macros.h"
#include "system.h"
#include "libdsp.h"
#include "main.h"

/****************************************************************************
 Include Section: SysControl
*****************************************************************************/

#if ( defined (__ADSPBF52x__) && ( __SILICON_REVISION__ >= 0x002 ) )  || ( defined (__ADSPBF54x__) && ( __SILICON_REVISION__ >= 0x001 ) )
    #if __VISUALDSPVERSION__ <= 0x05000200
        #include "bfrom.h"
    #else
        #include <bfrom.h>
    #endif
    .import "bfrom.h";
#endif

/****************************************************************************
 Include Section: System Initialization
*****************************************************************************/

#if defined __ADSPBF527__
    #include "ezkitBF527_initcode.h"
#endif

#if defined __ADSPBF533__
    /*************************************
    * ADSP-BF533/2/1 Sil. Rev. < 0.3     *
    * 05000070 - SDRAM PSSE bit cannot   *
    * be set again after SDRAM Powerup   *
    * Please check if required to enable *
    *************************************/
    //#define WORKAROUND_05000070
    #include "ezkitBF533_initcode.h"
#endif

#if defined __ADSPBF537__
    #include "ezkitBF537_initcode.h"
#endif

#if defined __ADSPBF538__
    #include "ezkitBF538_initcode.h"
#endif

#if defined __ADSPBF561__
    #include "ezkitBF561_initcode.h"
#endif

#if defined __ADSPBF548__
    #include "ezkitBF548_initcode.h"
#endif

/****************************************************************************
 Include Section: CPLB / Cache
*****************************************************************************/

#if defined INSTR_CACHE_EN
    #include "ICPLB.h"
#endif
#if defined DATA_CACHE_EN
    #include "DCPLB.h"
#endif

/*****************************************************************************
 Symbolic constants / definitions
******************************************************************************/

#define CORE_MMR_BASE           0xFFE00000
#define SYS_MMR_BASE            0xFFC00000

#if defined EN_SDRAM
    #if defined __ADSPBF54x__
        #define EN_DDRSDRAM
    #else
        #define EN_SDRSDRAM
    #endif
#endif

#define SYSCFG_VAL              0x30                        /* Program this value into SYSCFG register */

/*****************************************************************************
 Prototypes
******************************************************************************/

.GLOBAL __reset;


/*****************************************************************************
 Functions
******************************************************************************/

.SECTION L1_startup;


/****************************************************************************
 Function:      __reset
 
 Description:   Initialize System Configuration Register
*****************************************************************************/

__reset:

/****************************************************************************
 Description:   Set up supervisor stack
****************************************************************************/

IMM32(SP,0xFFB00800);
FP = SP;


/****************************************************************************
 Description:   Initialize System Configuration Register
****************************************************************************/

R7 = SYSCFG_VAL;
SYSCFG = R7;
IMM32(P5,SYS_MMR_BASE);


/*****************************************************************************
 Pre-Init Section
******************************************************************************/

/************************************************
* System Interrupt Wakeup Registers (SIC_IWRx)  *
* Required for PLL_CTL and VR_CTL configuration *
* Processor idle and wake up after PLL_LOCKCNT  *
* expired.Reset = 0xFFFF FFFF                   *
* disable all other interrupt sources in the    *
* meantime to disable unwanted wake up events   *
************************************************/

#if defined (SET_PLL) || defined (EN_SDRAM)

R7 = IWR_DISABLE_ALL;
#if defined __ADSPBF54x__
[P5 + lo(SIC_IWR2)] = R7;
#endif
#if defined (__ADSPBF52x__) || defined (__ADSPBF538__) || defined (__ADSPBF54x__) || defined (__ADSPBF561__)
[P5 + lo(SIC_IWR1)] = R7;
#endif
R7 = IRQ_PLL_WAKEUP;
[P5 + lo(SIC_IWR0)] = R7;  /* enable PLL Wakeup Interrupt */

#endif /* defined (SET_PLL) || defined (EN_SDRAM) */


/*****************************************************************************************
 Description:   Dynamic Power Managment
*****************************************************************************************/
DPM:
#if defined SET_PLL
    call __full_on;
#endif /* SET_PLL */


/*****************************************************************************
 Description:   Configure EBIU
******************************************************************************/
EBIU:


/*****************************************************************************
 Description:   Configure and enable asynchronous memory
******************************************************************************/
#if defined EN_ASYNC_MEM

/**********************************************
* Asynchronous Memory Bank Control 0 Register *
**********************************************/

IMM32(R7,EBIU_AMBCTL0_VAL);
[P5 + lo(EBIU_AMBCTL0)] = R7;


/**********************************************
* Asynchronous Memory Bank Control 1 Register *
**********************************************/

IMM32(R7,EBIU_AMBCTL1_VAL);
[P5 + lo(EBIU_AMBCTL1)] = R7;


/**********************************************
* Asynchronous Memory Global Control Register *
***********************************************/

R7.L = EBIU_AMGCTL_VAL;
w[P5 + lo(EBIU_AMGCTL)] = R7;

#endif /* EN_ASYNC_MEM */


/*****************************************************************************
Description:   Configure and enable SDRAM
******************************************************************************/
#if defined EN_SDRSDRAM

#if defined WORKAROUND_05000070
    R7 = w[P5 + lo(EBIU_SDSTAT)];
    CC = bittst(R7, bitpos(SDRS));
    if !CC jump skip_sdram_enable;
#endif


/*************************************
* SDRAM Memory Bank Control Register *
**************************************/

#if defined __ADSPBF561__
    IMM32(R7,EBIU_SDBCTL_VAL);
    [P5 + lo(EBIU_SDBCTL)] = R7;
#else
    R7.L = EBIU_SDBCTL_VAL;
    w[P5 + lo(EBIU_SDBCTL)] = R7;
#endif


/***************************************
* SDRAM Memory Global Control Register *
***************************************/

IMM32(R7,EBIU_SDGCTL_VAL);
[P5 + lo(EBIU_SDGCTL)] = R7;


#if defined WORKAROUND_05000070 /* see 'ezkitBF533_initcode.h' for more details */
    skip_sdram_enable: nop;
#endif


/***************************************************************************
* SDRAM Refresh Rate Control Register                                      *