adsp-bf5xx_asm.ldf

ADI公司SHARC与BlackFin通过SPI协议相互通信的源代码

/*****************************************************************************
**                                                                          **
**  Name:   LDF for Blackfin processors                                     **
**                                                                          **
******************************************************************************

 (C) Copyright 2006-2007 - Analog Devices, Inc.  All rights reserved.

 To place code/data to a specific address, use:
 RESOLVE (name, address)
 e.g.
 RESOLVE (src, 0xFF804000)
 RESOLVE (dst, 0xFF804800)

*****************************************************************************/


#include "configurations.h"
#include "Blackfin_Memory_Map.h"


#if defined __ADSPBF527__
    ARCHITECTURE(ADSP-BF527)
#elif defined __ADSPBF531__
    ARCHITECTURE(ADSP-BF531)
#elif  defined __ADSPBF532__
    ARCHITECTURE(ADSP-BF532)
#elif defined __ADSPBF533__
    ARCHITECTURE(ADSP-BF533)
#elif defined __ADSPBF534__
    ARCHITECTURE(ADSP-BF534)
#elif defined __ADSPBF536__
    ARCHITECTURE(ADSP-BF536)
#elif defined __ADSPBF537__
    ARCHITECTURE(ADSP-BF537)
#elif defined __ADSPBF538__
    ARCHITECTURE(ADSP-BF538)
#elif defined __ADSPBF539__
    ARCHITECTURE(ADSP-BF539)
#elif defined __ADSPBF548__
    ARCHITECTURE(ADSP-BF548)
#else
    ARCHITECTURE(I DON'T KNOW)
#endif


$OBJECTS = $COMMAND_LINE_OBJECTS;
$LIBRARIES = $COMMAND_LINE_OBJECTS;


MEMORY
{
//    MEM_CORE_MMRS       { TYPE(RAM) START(CORE_MMR_START) LENGTH(CORE_MMR_LENGTH) WIDTH(8) }    /* Core MMR Register 2MB */
    MEM_SYS_MMRS        { TYPE(RAM) START(SYS_MMR_START) LENGTH(SYS_MMR_LENGTH) WIDTH(8) }    /* System MMR Register 2MB */
    MEM_L1_SCRATCH      { TYPE(RAM) START(SCRATCH_START) LENGTH(SCRATCH_LENGTH) WIDTH(8) }    /* Scratchpad SRAM 4kB */



    #if !defined INSTR_CACHE_EN && !defined (__ADSPBF532__) && !defined (__ADSPBF533__) && !defined (__ADSPBF538__) && !defined (__ADSPBF539__)
     /* For these processors, these addresses are not seamless */
        CODE2           { TYPE(RAM) START(INSTR_CACHE_START) LENGTH(INSTR_CACHE_LENGTH) WIDTH(8) }    /* Instr. SRAM 16kB */
    #endif

    CODE                { TYPE(RAM) START(INSTR_SRAM_START) LENGTH(INSTR_SRAM_LENGTH) WIDTH(8) }



    #if defined (DATA_CACHE_EN) && defined (DATA_CACHE_AB)
        #if defined (__ADSPBF531__) || defined (__ADSPBF532__)
            /* Data Bank B SRAM 0kB */
        #else
            DATA_B_SRAM { TYPE(RAM) START(DATA_SRAM_B_START) LENGTH(DATA_SRAM_B_LENGTH) WIDTH(8) }    /* Data Bank B SRAM 16kB */
        #endif
    #else
        #if defined __ADSPBF531__
            /* Data Bank B SRAM 0kB */
        #else
            DATA_B_SRAM { TYPE(RAM) START(DATA_SRAM_B_START) LENGTH(DATA_SRAM_B_LENGTH) WIDTH(8) }    /* Data Bank B SRAM 32/16kB */
        #endif
    #endif



    #if defined DATA_CACHE_EN
        #if defined (__ADSPBF531__) || defined (__ADSPBF532__)
            /* Data Bank A SRAM 0kB */
        #else
            DATA_A_SRAM { TYPE(RAM) START(DATA_SRAM_A_START) LENGTH(DATA_SRAM_A_LENGTH) WIDTH(8) }    /* Data Bank A SRAM 16kB */
        #endif
    #else
        DATA_A_SRAM     { TYPE(RAM) START(DATA_SRAM_A_START) LENGTH(DATA_SRAM_A_LENGTH) WIDTH(8) }    /* Data Bank A SRAM 32/16kB */
    #endif



    #if defined __ADSPBF54x__
        CODE_ROM        { TYPE(ROM) START(INSTR_ROM_START) LENGTH(INSTR_ROM_LENGTH) WIDTH(8) }  /* Instr. ROM 64kB */
        L2_SRAM         { TYPE(RAM) START(L2_SRAM_START)   LENGTH(L2_SRAM_LENGTH)   WIDTH(8) }  /* L2 SRAM 128kB */
        ASYNC_MEM_0     { TYPE(RAM) START(0x20000000)      END(0x21FFFFFF)          WIDTH(8) }  /* 32MB Burst/NOR FLASH memory */
    #else
        ASYNC_MEM_3     { TYPE(RAM) START(0x20300000) END(0x203FFFFF) WIDTH(8) }    /* 1MB */
        ASYNC_MEM_2     { TYPE(RAM) START(0x20200000) END(0x202FFFFF) WIDTH(8) }    /* 1MB */
        ASYNC_MEM_1     { TYPE(RAM) START(0x20100000) END(0x201FFFFF) WIDTH(8) }    /* 1MB */
        ASYNC_MEM_0     { TYPE(RAM) START(0x20000000) END(0x200FFFFF) WIDTH(8) }    /* 1MB */
    #endif



    #if defined SDRAM_SIZE
        SDRAM_MEM       { TYPE(RAM) START(0x00000000) LENGTH(SDRAM_LENGTH) WIDTH(8) }
    #endif /* defined SDRAM_SIZE */
}


PROCESSOR p0
{
    OUTPUT( $COMMAND_LINE_OUTPUT_FILE )

    RESOLVE( __reset, INSTR_SRAM_START )
    KEEP( __reset )


    #if defined USE_LDF_RESOLVE
        #include "LDF_RESOLVE.h"
    #endif


    SECTIONS
    {

//        #if !defined INSTR_CACHE_EN && !defined (__ADSPBF532__) && !defined (__ADSPBF533__) && !defined (__ADSPBF538__) && !defined (__ADSPBF539__)
        #if !defined INSTR_CACHE_EN && defined (__ADSPBF531__) && defined (__ADSPBF534__) && defined (__ADSPBF536__) && defined (__ADSPBF537__) && defined (__ADSPBF52x__) && defined (__ADSPBF54x__)
        code2
            {
                INPUT_SECTION_ALIGN(4)
                INPUT_SECTIONS($OBJECTS(program))
                INPUT_SECTIONS($OBJECTS(L1_code))
                INPUT_SECTIONS($OBJECTS(cplb_code) $LIBRARIES(cplb_code))
            } > CODE2
        #endif


        code
        {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS($OBJECTS(program))
            INPUT_SECTIONS($OBJECTS(L1_code))
            INPUT_SECTIONS($OBJECTS(L1_startup))
            INPUT_SECTIONS($OBJECTS(cplb_code) $LIBRARIES(cplb_code))
        } > CODE


        #if defined __ADSPBF531__
            /* no DATA_B_SRAM at all */
        #elif defined (__ADSPBF532__) && defined (DATA_CACHE_EN) && defined (DATA_CACHE_AB)
            /* no DATA_B_SRAM -> Cache only */
        #else
            data_b_sram
            {
                FORCE_CONTIGUITY
                INPUT_SECTION_ALIGN(4)
                INPUT_SECTIONS($OBJECTS(L1_data))
                INPUT_SECTIONS($OBJECTS(L1_data_b))
                INPUT_SECTIONS($OBJECTS(cplb_data) $LIBRARIES(cplb_data))
            } > DATA_B_SRAM
        #endif


        #if defined (__ADSPBF531__) && defined (DATA_CACHE_EN)
            /* no DATA_A_SRAM -> Cache only */
        #elif defined (__ADSPBF532__) && defined (DATA_CACHE_EN)
            /* no DATA_A_SRAM -> Cache only */
        #else
            data_a_sram
            {
                FORCE_CONTIGUITY
                INPUT_SECTION_ALIGN(4)
                INPUT_SECTIONS($OBJECTS(L1_data))
                INPUT_SECTIONS($OBJECTS(L1_data_a))
                INPUT_SECTIONS($OBJECTS(cplb_data) $LIBRARIES(cplb_data))
            } > DATA_A_SRAM
        #endif


        #if defined __ADSPBF54x__

            L2_SRAM// NO_INIT
            {
                FORCE_CONTIGUITY
                INPUT_SECTION_ALIGN(4)
                INPUT_SECTIONS($OBJECTS(program))
                INPUT_SECTIONS($OBJECTS(L2_code))
                INPUT_SECTIONS($OBJECTS(L2_data))
                INPUT_SECTIONS($OBJECTS(L2_sram))
                INPUT_SECTIONS($OBJECTS(sram))
                INPUT_SECTIONS($OBJECTS(cplb_data) $LIBRARIES(cplb_data))
            } > L2_SRAM

        #endif


        #if defined SDRAM_SIZE

            SDRAM// NO_INIT
            {
                FORCE_CONTIGUITY
                INPUT_SECTION_ALIGN(4)
                INPUT_SECTIONS($OBJECTS(program))
                INPUT_SECTIONS($OBJECTS(sdram))
                INPUT_SECTIONS($OBJECTS(cplb_data) $LIBRARIES(cplb_data))
            } > SDRAM_MEM

        #endif

    }
}