📄 init.asm
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/****************************************************************************
Include Section
*****************************************************************************/
#include "global.h"
#include "IVGx_handler.h"
/*****************************************************************************
Symbolic constants / definitions
******************************************************************************/
#define SPISSEL7 PJ5
#define SPISSEL6 PF4 /* /PFHW */
#define SPISSEL5 PF5
#define SPISSEL4 PF6 /* EZ-KIT LED1 */
#define SPISSEL3 PJ10
#define SPISSEL2 PJ11
#define SPISSEL1 PF10 /* EZ-KIT LED5 */
#define SPIMOSI PF11 /* EZ-KIT LED6 */
#define SPIMISO PF12
#define SPISCK PF13
#define SPISS PF14
/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
/* SIC_IARx Macros */
/* x = 0 to 9 */
#define PIVG(PNr, IVGNr) ( (IVGNr) - 7) << ( ((PNr)%8) *4) /* Peripheral #PNr assigned IVG #IVGNr */
/* Rx.L = lo(PIVG(62,10)); */
/* Rx.H = hi(PIVG(62,10)); */
/* PNr = 0 to 95 */
/* IVGNr = 7 to 15 */
#define SIC_IARx(x) ( 0xF<<(4*x))
#define nSIC_IARx(x) (~(0xF<<(4*x)))
/*****************************************************************************
Prototypes
******************************************************************************/
.GLOBAL __interrupts_setup;
.GLOBAL __gpio_ports_setup;
/*****************************************************************************
Functions
******************************************************************************/
.SECTION L1_code;
/****************************************************************************
Function: __gpio_ports_setup
Description: setup up general purpose ports
GPIO PORT F:
SPI MOSI -> GPIO PF11 EZ-KIT LED6
SPI MISO -> GPIO PF12
SPI SCK -> GPIO PF13
SPI SS -> GPIO PF14
SPI SSEL6 -> GPIO PF4 /HW
SPI SSEL5 -> GPIO PF5
SPI SSEL4 -> GPIO PF6 EZ-KIT LED1
SPI SSEL1 -> GPIO PF10 EZ-KIT LED5
GPIO PORT J:
SPI SSEL7 -> GPIO PJ5
SPI SSEL3 -> GPIO PJ10
SPI SSEL2 -> GPIO PJ11
PORT_MUX MASKS:
PJSE_SPI -> Enable SPI_SSEL3:2
PFS4E_SPI -> Enable SPI_SSEL4
PFS5E_SPI -> Enable SPI_SSEL5
PFS6E_SPI -> Enable SPI_SSEL6
PJCE_SPI -> Enable SPI_SSEL7
Input Parameters: none
Return Parameters: none
Registers Used: R7:6,P5
Global Variables Used: none
C-Callable : no
*****************************************************************************/
__gpio_ports_setup:
link 0;
[--SP] = (R7:6,P5:5);
IMM32(P5,SYS_MMR_BASE);
/*****************************************************************************
ADSP-BF537 HRM:
The SPISS signal can connect to the PF14 pin which functions as a GPIO by
default. To enable this pin for use as the SPI slave-select input signal,
be sure to first configure the PORTF_FER register to enable the PF14 pin
for peripheral use (see 'Function Enable Registers' on page 14-23), and
then set the PORT_MUX register to specifically enable the SPI slave select
input functionality (see 'Port Multiplexer Control Register' on page 14-22).
*****************************************************************************/
/* function enable registers, for all bits: 0 - GPIO mode, 1 - enable peripheral function */
/* set port f function enable register (need workaround) */
R7 = 0x0 (z);
R6 = w[P5 + lo(PORTF_FER)] (z); /* #22 work-around, read PORT_MUX before writing */
ssync;
w[P5 + lo(PORTF_FER)] = R7; /* #22 work-around: write it a few times */
ssync;
w[P5 + lo(PORTF_FER)] = R7; /* #22 work-around: write it a few times */
ssync;
/* set port f clear register */
R7.L = 0xFFFF;
w[P5 + lo(PORTFIO_CLEAR)] = R7;
#if defined SPI_MASTER_MODE
/* Function Enable Registers: For all bits, 0 - GPIO mode, 1 - Enable Peripheral function */
R7 = ( SPIMOSI | SPIMISO | SPISCK ) (z);
R6 = 0 (z);
#if SPI_SLAVE == 1
bitset(R7,bitpos(SPISSEL1));
#endif
#if SPI_SLAVE == 2
R6 = PJSE_SPI (z);
#endif
#if SPI_SLAVE == 3
R6 = PJSE_SPI (z);
#endif
#if SPI_SLAVE == 4
R6 = PFS4E_SPI (z);
bitset(R7,bitpos(SPISSEL4));
#endif
#if SPI_SLAVE == 5
R6 = PFS5E_SPI (z);
bitset(R7,bitpos(SPISSEL5));
#endif
#if SPI_SLAVE == 6
R6 = PFS6E_SPI (z);
bitset(R7,bitpos(SPISSEL6));
#endif
#if SPI_SLAVE == 7
R6 = PJCE_SPI (z);
#endif
#if SPI_SLAVE != 1
w[P5 + lo(PORT_MUX)] = R6;
ssync;
#endif
w[P5 + lo(PORTF_FER)] = R7;
ssync;
/* hostwait master input */
#if defined PFHW
R7 = w[P5 + lo(PORTFIO_DIR)](z);
bitclr(R7,bitpos(PFHW));
w[P5 + lo(PORTFIO_DIR)] = R7;
R7 = w[P5 + lo(PORTFIO_POLAR)](z);
bitclr(R7,bitpos(PFHW));
w[P5 + lo(PORTFIO_POLAR)] = R7;
R7 = w[P5 + lo(PORTFIO_INEN)](z);
bitset(R7,bitpos(PFHW));
w[P5 + lo(PORTFIO_INEN)] = R7;
#endif
#endif /* SPI_MASTER_MODE */
#if defined SPI_SLAVE_MODE
/* Function Enable Registers: For all bits, 0 - GPIO mode, 1 - Enable Peripheral function */
R7 = ( SPIMOSI | SPIMISO | SPISCK | SPISS ) (z);
w[P5 + lo(PORTF_FER)] = R7;
#if defined PFHW
/* hostwait slave output */
R7 = w[P5 + lo(PORTFIO_DIR)](z);
bitset(R7,bitpos(PFHW));
w[P5 + lo(PORTFIO_DIR)] = R7;
#endif
#endif /* SPI_SLAVE_MODE */
call __led_all_turn_off;
(R7:6,P5:5) = [SP++];
unlink;
rts;
__gpio_ports_setup.END:
/****************************************************************************
Function: __interrupts_setup
Description: assign peripheral #2 (SPI error) to IVG7
assign peripheral #10 (IRQ_DMA7 / SPI data) to IVG10
enable IVG7
enable IVG10
GP Interrupt SIC_IAR value
IVG7 0
IVG8 1
IVG9 2
IVG10 3
IVG11 4
IVG12 5
IVG13 6
IVG14 7
IVG15 8
Input Parameters: none
Return Parameters: none
Registers Used: R7:6,P5
Global Variables Used: none
C-Callable : no
*****************************************************************************/
__interrupts_setup:
link 0;
[--SP] = (R7:6,P5:5);
IMM32(P5,SYS_MMR_BASE);
/* System Interrupt Assignment Registers (SIC_IARx): Sets relative priority of peripheral interrupts by mapping the peripheral interupts to the appropriate general-purpose interrupt level in the core */
R7 = [P5 + lo(SIC_IAR0)];
IMM32(R6,nSIC_IARx(2));
R7 = R7 & R6;
IMM32(R6,PIVG(2,7));
R7 = R7 | R6;
[P5 + lo(SIC_IAR0)] = R7;
/* SPI_CORE_LOOP mode requires no interrupts -> it polls status bits only */
#if defined SPI_DMA
R7 = [P5 + lo(SIC_IAR1)];
IMM32(R6,nSIC_IARx(2));
R7 = R7 & R6;
IMM32(R6,PIVG(10,10));
R7 = R7 | R6;
[P5 + lo(SIC_IAR1)] = R7;
#endif
/* System Interrupt Mask Register (SIC_IMASK): Writing a 1 to a bit loacation turns off the mask and enables the interrupt */
R7 = [P5 + lo(SIC_IMASK)];
#if defined SPI_DMA
R6 = ( IRQ_ERROR2 | IRQ_DMA7 ) (z);
#else
R6 = ( IRQ_ERROR2 ) (z);
#endif
R7 = R7 | R6;
[P5 + lo(SIC_IMASK)] = R7;
/* Event Vector Registers */
IMM32(P5,CORE_MMR_BASE);
IMM32(R7,__ivg7_handler);
[P5 + lo(EVT7)] = R7;
IMM32(R7,__ivg10_handler);
[P5 + lo(EVT10)] = R7;
/* Core Interrupt Mask Register (IMASK): Indikates, which interrupt levels are allowed to be taken. */
R7 = [P5 + lo(IMASK)];
#if defined SPI_DMA
R6 = ( EVT_IVG7 | EVT_IVG10 ) (z);
#else
R6 = ( EVT_IVG7 ) (z);
#endif
R7 = R7 | R6;
[P5 + lo(IMASK)] = R7;
(R7:6,P5:5) = [SP++];
unlink;
rts;
__interrupts_setup.END:
/*****************************************************************************
EOF
******************************************************************************/
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