configurations.h

ADI公司SHARC与BlackFin通过SPI协议相互通信的源代码

/********************************************************************************
 System Setup Define Section
 
 Comment out (please don't delete) the ones that do not apply to your code
********************************************************************************/


/*****************************************************************************
 Symbolic constants / definitions
******************************************************************************/


/****************************************************************************
* The following option is always required, if SDRAM memory is required:     *
*           #define EN_ASYNC_MEM        --> Enable asynchronous memory      *
*           #define EN_SDRAM            --> Enable SDRAM memory             *
*                                       usually NOT required                *
*                                       either VDSP++/Emulator is doing     *
*                                       these settings or init code         *
*           #define SDRAM_SIZE xy       Available options for xy are:       *
*                                       128 --> SDRAM memory size = 128 MB  *
*                                        64 --> SDRAM memory size =  64 MB  *
*                                        32 --> SDRAM memory size =  32 MB  *
*           #define SET_PLL             --> Change default (reset) PLL and  *
*                                       voltage controller settings         *
****************************************************************************/

//#define             EN_ASYNC_MEM
//#define             EN_SDRAM
#define             SET_PLL

//#define             SDRAM_SIZE      64


/************************************************************
* Otherwise code is run in supervisor mode ISR15 by default *
************************************************************/

//#define             RUN_USER


/************************************************************************************
* SPI modes                                                                         *
* Possible options are:                                                             *
* (please choose MAXIMUM ONE of the following options at the same time)             *
*           no definition                       --> DEFAULT MODE: SPI DMA transfer  *
*                                                   interrupts enabled: YES         *
*           #define SPI_DMA                     --> DEFAULT MODE: SPI DMA transfer  *
*                                                   interrupts enabled: YES         *
*           #define SPI_CORE_LOOP               --> CORE is used for SPI transfer   *
*                                                   interrupts enabled: NO          *
*                                                   Core is polling the SPI status  *
************************************************************************************/

#define             SPI_DMA
//#define             SPI_CORE_LOOP


/****************************************************************************
* SPI transfer mode                                                         *
* (please choose ONLY ONE of the following options at the same time)        *
*           #define SPI_MODE_TRC            Transmit->Receive->Compare      *
*           #define SPI_MODE_RCT            Receive->Copy->Transmit         *
*           #define SPI_TRANSMIT            Transmit only                   *
*           #define SPI_RECEIVE             Receive only                    *
****************************************************************************/

//#define             SPI_MODE_TRC
//#define             SPI_MODE_RCT
#define             SPI_TRANSMIT
//#define             SPI_RECEIVE


/************************************************************************************
* SPI configurations                                                                *
* Possible options are:                                                             *
*           #define SPI_CPOL_LOW            --> Clock Polarity: Active low SCK      *
*                                           default: Active high SCK                *
*           #define SPI_CPHA                --> Clock Phase: SCK toggles from       *
*                                               beginning of the first bit          *
*                                           default: SCK toggles from middle        *
*                                               of the first data bit               *
*           #define SPI_LSBF                --> LSB sent/receive first              *
*                                           default: MSB sent/receive first         *
*           #define SPI_WDSIZE_16            --> word size is 16 bit                *
*                                           applies NOT to SPI modes:               *
*                                           - SPI_CORE_NO_INTERRUPT                 *
*                                           default: word size is 8 bit             *
*           #define SPI_SZ                  --> send zeros                          *
*                                           Send zero or last word when             *
*                                           SPI_TDBR is empty                       *
*                                           default: Send last word                 *
*           #define SPI_GM                  --> Get more data, overwrite prev. data *
*                                           When SPI_RDBR is full, get data         *
*                                           or discard incoming data                *
*                                           default: Discard incoming data          *
*           #define PHHW                    select pin for /HOSTWAIT signal         *
*                                           /HOSTWAIT is active low                 *
*                                           Master: PFHW is intput                  *
*                                           HOSTWAIT signal is checked before a     *
*                                           transfer is started but not between     *
*                                           every single data word                  *
*                                           Slave:  PFHW is output                  *
*                                           This feature is not supported on the    *
*                                           SHARC project                           *
************************************************************************************/

//#define             SPI_CPOL_LOW
//#define             SPI_CPHA

//#define             SPI_LSBF
#define             SPI_WDSIZE_16

//#define             SPI_SZ
//#define             SPI_GM

//#define             PFHW                PF4 /* PF4_PB3 -> EZ-KIT Lite SW5-3 [OFF] */


/****************************************
* Do not modify !!!                     *
* There are some parts left in the code *
* that need exactly these definitions   *
****************************************/

#if !defined SPI_SLAVE_MODE
    #define SPI_SLAVE_MODE
#endif
#undef SPI_MASTER_MODE

#if !defined (SPI_DMA) && !defined (SPI_CORE_LOOP)
#define SPI_DMA
#endif
#if defined SPI_DMA
#undef SPI_CORE_LOOP
#endif


/*****************************************************************************
 EOF
******************************************************************************/