initpll.asm

ADI公司SHARC与BlackFin通过SPI协议相互通信的源代码

#include <def21369.h>
#include "SPI.h"

.global InitPLL;
.global core_speed;

.section/dm seg_dmda;
.var core_speed = 147456000;

.section/pm seg_pmco;
InitPLL:
#ifdef MAX_CORE_CLOCK      //PLLM27 & Input Divider Enabled (24.576 * 27 / 2)
		// CLKIN= 24.576 MHz, Multiplier= 27, Divisor= 2, CCLK_SDCLK_RATIO 2.
// Core clock = (24.576MHz * 27) /2 = 331.776 MHz
    ustat3 = PLLM27|INDIV|DIVEN;
    r0 = 331776000;
    dm(core_speed) = r0;
    
#endif

#ifdef PLL_319_MHZ		 //PLLM13 (24.576 * 13)
    ustat3 = PLLM13|DIVEN;
    
    r0 = 319488000;
    dm(core_speed) = r0;
    
#endif    

#ifdef PLL_294_MHZ		 //PLLM12 (24.576 * 12)
    ustat3 = PLLM12|DIVEN;
    
    r0 = 294912000;
    dm(core_speed) = r0;
    
#endif    

#ifdef PLL_270_MHZ		 //PLLM11 (24.576 * 11)
    ustat3 = PLLM11|DIVEN;
    
    r0 = 270336000;
    dm(core_speed) = r0;
    
#endif    

#ifdef PLL_240_MHZ		 //PLLM10 (24.576 * 10)
    ustat3 = PLLM10|DIVEN;
    
    r0 = 245760000;
    dm(core_speed) = r0;
    
#endif    

#ifdef PLL_221_MHZ		 //PLLM9 (24.576 * 9)
    ustat3 = PLLM9|DIVEN;
    
    r0 = 221184000;
    dm(core_speed) = r0;
    
#endif    

#ifdef PLL_196_MHZ		 //PLLM8 (24.576 * 8)
    ustat3 = PLLM8|DIVEN;
    
    r0 = 196608000;
    dm(core_speed) = r0;
    
#endif    

#ifdef PLL_172_MHZ		 //PLLM7 (24.576 * 7)
    ustat3 = PLLM7|DIVEN;
    
    r0 = 172032000;
    dm(core_speed) = r0;
    
#endif    

#ifdef PLL_147_MHZ		 //PLLM6 (24.576 * 6)
    ustat3 = PLLM6|DIVEN;
    
    r0 = 147456000;
    dm(core_speed) = r0;
    
#endif    

#ifdef MIN_CORE_CLOCK		 //PLLM5 (24.576 * 5)
    ustat3 = PLLM5|DIVEN;
    
    r0 = 122880000;
    dm(core_speed) = r0;
    
#endif    

changePLL:

    // Set the Core clock (CCLK) to SDRAM clock (SDCLK) ratio to 2
   bit set ustat3 SDCKR2;

    dm(PMCTL) = ustat3;
    bit set ustat3 PLLBP; //Place the PLL in bypass mode.
	bit clr ustat3 DIVEN; //Clear the DIVEN bit while placing the PLL in bypass mode.
    dm(PMCTL) = ustat3;

     // Wait for at least 4096 cycles for the pll to lock
    lcntr = 5000, do loopend2 until lce;
loopend2:     nop;

    ustat3 = dm(PMCTL);	//Reading the PMCTL register will return the DIVEN bit value as zero.
    bit clr ustat3 PLLBP; //Take the PLL out of bypass mode.
    dm(PMCTL) = ustat3;
	
InitPLL.end: rts;