spi.h

ADI公司SHARC与BlackFin通过SPI协议相互通信的源代码

//#define SET_CPHASE	//uncomment this to configure SPI with CPHASE = 1 and CLKPL = 0
//#define SET_CLKPL       //uncomment this to configure SPI with CPHASE = 0 and CLKPL = 1
//#define SET_CPHASE_CLKPL //uncomment this to configure SPI with CPHASE = 1 and CLKPL = 1
						   // When all the above statements are commented SPI is configured with CPHASE = 0 and CLKPL = 0

#define SL_TRANSMITTER  //Uncomment this to use the master to transmit in DMA mode
						  //Comment this to use the master to receive in DMA mode


// Configure PLL Frequency uncomment one of the below at any time
// Clkin = 24.576MHz

#define MAX_CORE_CLOCK      //PLLM27 & Input Divider Enabled (24.576 * 27 / 2)
//#define PLL_319_MHZ		 //PLLM13 (24.576 * 13)
//#define PLL_294_MHZ		 //PLLM12 (24.576 * 12)
//#define PLL_270_MHZ		 //PLLM11 (24.576 * 11)
//#define PLL_240_MHZ		 //PLLM10 (24.576 * 10)
//#define PLL_221_MHZ		 //PLLM9  (24.576 * 9)
//#define PLL_196_MHZ		 //PLLM8  (24.576 * 8)
//#define PLL_172_MHZ		 //PLLM7  (24.576 * 7)
//#define PLL_147_MHZ		 //PLLM6  (24.576 * 6)
//#define MIN_CORE_CLOCK	 //PLLM5  (24.576 * 5)