复件 2440init.s
来自「移植好的UCOS2.86版」· S 代码 · 共 895 行 · 第 1/2 页
S
895 行
;//=========================================
;// NAME: 2440INIT.S
;// DESC: C start up codes
;// Configure memory, ISR ,stacks
;// Initialize C-variables
;// HISTORY:
;// 2002.02.25:kwtark: ver 0.0
;// 2002.03.20:purnnamu: Add some functions for testing STOP,Sleep mode
;// 2003.03.14:DonGo: Modified for 2440.
;//=========================================
GET option.inc
GET memcfg.inc
GET 2440addr.inc
BIT_SELFREFRESH EQU (1<<22)
;//Pre-defined constants
USERMODE EQU 0x10
FIQMODE EQU 0x11
IRQMODE EQU 0x12
SVCMODE EQU 0x13
ABORTMODE EQU 0x17
UNDEFMODE EQU 0x1b
MODEMASK EQU 0x1f
NOINT EQU 0xc0
;//The location of stacks (_STACK_BASEADDRESS EQU 0x33ff8000)
UserStack EQU (_STACK_BASEADDRESS-0x3800) ;//0x33ff4800 ~
SVCStack EQU (_STACK_BASEADDRESS-0x2800) ;//0x33ff5800 ~
UndefStack EQU (_STACK_BASEADDRESS-0x2400) ;//0x33ff5c00 ~
AbortStack EQU (_STACK_BASEADDRESS-0x2000) ;//0x33ff6000 ~
IRQStack EQU (_STACK_BASEADDRESS-0x1000) ;//0x33ff7000 ~
FIQStack EQU (_STACK_BASEADDRESS-0x0) ;//0x33ff8000 ~
;//code16伪指令指示汇编编译器后面的指令为16位的thumb指令
;//code32伪指令指示汇编编译器后面的指令为32位的arm指令
;//这段是为了统一目前的处理器工作状态和软件编译方式（16位编译环境使用tasm.exe编译
;//Check if tasm.exe(armasm -16 ...@ADS 1.0) is used.
GBLL THUMBCODE ;//定义一个全局变量
[ {CONFIG} = 16 ;//if config==16 这里表示你的目前处于领先地16位编译方式
THUMBCODE SETL {TRUE} ;//设置THUMBCODE 为 true表示告诉系统当前想用thumb，但实际启动时不行，只能启动后再跳
;//[|]表示#if #else #endif
CODE32 ;//启动时强制使用32位编译模式
|
THUMBCODE SETL {FALSE} ;//如果系统要求是ARM指令，则直接设置THUMBCODE 为 false 说明当前的是32位编译模式
]
MACRO ;//宏定义开始
MOV_PC_LR
[ THUMBCODE
bx lr ;//在ARM模式中要使用BX指令转跳到THUMB指令,并转换模式
|
mov pc,lr
]
MEND ;//宏定义结束
MACRO ;//和上面的宏一样,只是多了一个相等的条件
MOVEQ_PC_LR
[ THUMBCODE
bxeq lr ;//相等Z=1,则跳转
|
moveq pc,lr
]
MEND
;//下面包含的HandlerXXX HANDLER HandleXXX将都被下面这段程序展开。
;//向量中断模式是当cpu读取位于0x18处的IRQ中断指令的时候，系统自动读取对应于该中断源确定地址上的;
;//指令取代0x18处的指令，通过跳转指令系统就直接跳转到对应地址函数中 节省了中断处理时间提高了中断
;//处理速度标 例如 ADC中断的向量地址为0xC0,则在0xC0处放如下
;//非向量中断模式处理方式是一种传统的中断处理方法，当系统产生中断的时候，系统将interrupt
;//pending寄存器中对应标志位置位 然后跳转到位于0x18处的统一中断
;//函数中 该函数通过读取interrupt pending寄存器中对应标志位 来判断中断源 并根据优先级关系再跳到
;//对应中断源的处理代码中
MACRO
$HandlerLabel HANDLER $HandleLabel
$HandlerLabel
sub sp,sp,#4 ;//decrement sp(to store jump address)
stmfd sp!,{r0} ;//PUSH the work register to stack(lr does't' push because it return to original address)
ldr r0,=$HandleLabel;//load the address of HandleXXX to r0
ldr r0,[r0] ;//load the contents(service routine start address) of HandleXXX
str r0,[sp,#4] ;//store the contents(ISR) of HandleXXX to stack
ldmfd sp!,{r0,pc} ;//POP the work register and pc(jump to ISR)
MEND
IMPORT |Image$$RO$$Base| ;// Base of ROM code
IMPORT |Image$$RO$$Limit| ;// End of ROM code (=start of ROM data)
IMPORT |Image$$RW$$Base| ;// Base of RAM to initialise
IMPORT |Image$$ZI$$Base| ;// Base and limit of area
IMPORT |Image$$ZI$$Limit| ;// to zero initialise
IMPORT MMU_SetAsyncBusMode
IMPORT MMU_SetFastBusMode ;//hzh
IMPORT Main ;// The main entry of mon program
AREA Init,CODE,READONLY
ENTRY
EXPORT HandleEINT0 ;//for os_cpu_a.s
EXPORT __ENTRY
__ENTRY
ResetEntry
;//1)The code, which converts to Big-endian, should be in little endian code.
;//2)The following little endian code will be compiled in Big-Endian mode.
;// The code byte order should be changed as the memory bus width.
;//3)The pseudo instruction,DCD can't' be used here because the linker generates error.
ASSERT :DEF:ENDIAN_CHANGE
[ ENDIAN_CHANGE
ASSERT :DEF:ENTRY_BUS_WIDTH
[ ENTRY_BUS_WIDTH=32
b ChangeBigEndian ;//DCD 0xea000007
]
[ ENTRY_BUS_WIDTH=16
andeq r14,r7,r0,lsl #20 ;//DCD 0x0007ea00
]
[ ENTRY_BUS_WIDTH=8
streq r0,[r0,-r10,ror #1] ;//DCD 0x070000ea
]
|
b ResetHandler
]
b HandlerUndef ;//handler for Undefined mode
b HandlerSWI ;//handler for SWI interrupt
b HandlerPabort ;//handler for PAbort
b HandlerDabort ;//handler for DAbort
b . ;//reserved
b HandlerIRQ ;//handler for IRQ interrupt
b HandlerFIQ ;//handler for FIQ interrupt
;//@0x20
b EnterPWDN ;// Must be @0x20.
ChangeBigEndian
;//@0x24
[ ENTRY_BUS_WIDTH=32
DCD 0xee110f10 ;//0xee110f10 => mrc p15,0,r0,c1,c0,0
DCD 0xe3800080 ;//0xe3800080 => orr r0,r0,#0x80;// //Big-endian
DCD 0xee010f10 ;//0xee010f10 => mcr p15,0,r0,c1,c0,0
]
[ ENTRY_BUS_WIDTH=16
DCD 0x0f10ee11
DCD 0x0080e380
DCD 0x0f10ee01
]
[ ENTRY_BUS_WIDTH=8
DCD 0x100f11ee
DCD 0x800080e3
DCD 0x100f01ee
]
DCD 0xffffffff ;//swinv 0xffffff is similar with NOP and run well in both endian mode.
DCD 0xffffffff
DCD 0xffffffff
DCD 0xffffffff
DCD 0xffffffff
b ResetHandler
HandlerFIQ HANDLER HandleFIQ
HandlerIRQ HANDLER HandleIRQ
HandlerUndef HANDLER HandleUndef
HandlerSWI HANDLER HandleSWI
HandlerDabort HANDLER HandleDabort
HandlerPabort HANDLER HandlePabort
IsrIRQ
sub sp,sp,#4 ;//reserved for PC
stmfd sp!,{r8-r9}
ldr r9,=INTOFFSET
ldr r9,[r9]
ldr r8,=HandleEINT0
add r8,r8,r9,lsl #2
ldr r8,[r8]
str r8,[sp,#8]
ldmfd sp!,{r8-r9,pc}
LTORG
;//=======
;// ENTRY
;//=======
ResetHandler
ldr r0,=WTCON ;//watch dog disable
ldr r1,=0x0
str r1,[r0]
ldr r0,=INTMSK
ldr r1,=0xffffffff ;//all interrupt disable
str r1,[r0]
ldr r0,=INTSUBMSK
ldr r1,=0x7fff ;//all sub interrupt disable
str r1,[r0]
[ {FALSE}
;// rGPFDAT = (rGPFDAT & ~(0xf<<4)) | ((~data & 0xf)<<4);//
;// Led_Display
ldr r0,=GPFCON
ldr r1,=0x5500
str r1,[r0]
ldr r0,=GPFDAT
ldr r1,=0x10
str r1,[r0]
]
;//To reduce PLL lock time, adjust the LOCKTIME register.
ldr r0,=LOCKTIME
ldr r1,=0xffffff
str r1,[r0]
[ PLL_ON_START
;// Added for confirm clock divide. for 2440.
;// Setting value Fclk:Hclk:Pclk
ldr r0,=CLKDIVN
ldr r1,=CLKDIV_VAL ;// 0=1:1:1, 1=1:1:2, 2=1:2:2, 3=1:2:4, 4=1:4:4, 5=1:4:8, 6=1:3:3, 7=1:3:6.
str r1,[r0]
;// MMU_SetAsyncBusMode and MMU_SetFastBusMode over 4K, so dont'' call here
;// call it after copy, hzh
;// [ CLKDIV_VAL>1 ;// means Fclk:Hclk is not 1:1.
;// bl MMU_SetAsyncBusMode
;// |
;// bl MMU_SetFastBusMode ;// default value.
;// ]
;//program has not been copied, so use these directly, hzh
[ CLKDIV_VAL>1 ;// means Fclk:Hclk is not 1:1.
mrc p15,0,r0,c1,c0,0
orr r0,r0,#0xc0000000;//R1_nF:OR:R1_iA
mcr p15,0,r0,c1,c0,0
|
mrc p15,0,r0,c1,c0,0
bic r0,r0,#0xc0000000;//R1_iA:OR:R1_nF
mcr p15,0,r0,c1,c0,0
]
;//Configure UPLL
ldr r0,=UPLLCON
ldr r1,=((U_MDIV<<12)+(U_PDIV<<4)+U_SDIV)
str r1,[r0]
nop ;// Caution: After UPLL setting, at least 7-clocks delay must be inserted for setting hardware be completed.
nop
nop
nop
nop
nop
nop
;//Configure MPLL
ldr r0,=MPLLCON
ldr r1,=((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV) ;//Fin=16.9344MHz
str r1,[r0]
]
;//Check if the boot is caused by the wake-up from SLEEP mode.
ldr r1,=GSTATUS2
ldr r0,[r1]
tst r0,#0x2
;//In case of the wake-up from SLEEP mode, go to SLEEP_WAKEUP handler.
bne WAKEUP_SLEEP
EXPORT StartPointAfterSleepWakeUp
StartPointAfterSleepWakeUp
;//Set memory control registers
;//ldr r0,=SMRDATA
adrl r0, SMRDATA ;//be careful!, hzh
ldr r1,=BWSCON ;//BWSCON Address
add r2, r0, #52 ;//End address of SMRDATA
0
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne %B0
;//===delay, hzh
mov r0, #&1000
1
subs r0, r0, #1
bne %B1
;//===
;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//
;//;//;//;//;//;//;//;//;//;//;//;//;// When EINT0 is pressed, Clear SDRAM
;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//;//
;// check if EIN0 button is pressed
ldr r0,=GPFCON
ldr r1,=0x0
str r1,[r0]
ldr r0,=GPFUP
ldr r1,=0xff
str r1,[r0]
ldr r1,=GPFDAT
ldr r0,[r1]
bic r0,r0,#(0x1e<<1) ;// bit clear
tst r0,#0x1
bne %F1
;// Clear SDRAM Start
ldr r0,=GPFCON
ldr r1,=0x55aa
str r1,[r0]
;// ldr r0,=GPFUP
;// ldr r1,=0xff
;// str r1,[r0]
ldr r0,=GPFDAT
ldr r1,=0x0
str r1,[r0] ;//LED=****
mov r1,#0
mov r2,#0
mov r3,#0
mov r4,#0
mov r5,#0
mov r6,#0
mov r7,#0
mov r8,#0
ldr r9,=0x4000000 ;//64MB
ldr r0,=0x30000000
0
stmia r0!,{r1-r8}
subs r9,r9,#32
bne %B0
;//Clear SDRAM End
1
;//Initialize stacks
bl InitStacks
;//===========================================================
ldr r0, =BWSCON
ldr r0, [r0]
ands r0, r0, #6 ;//OM[1:0] != 0, NOR FLash boot
bne copy_proc_beg ;//don't' read nand flash
adr r0, ResetEntry ;//OM[1:0] == 0, NAND FLash boot
cmp r0, #0 ;//if use Multi-ice,
bne copy_proc_beg ;//don't' read nand flash for boot
;//nop
;//===========================================================
nand_boot_beg
mov r5, #NFCONF
;//set timing value
ldr r0, =(7<<12)|(7<<8)|(7<<4)
str r0, [r5]
;//enable control
ldr r0, =(0<<13)|(0<<12)|(0<<10)|(0<<9)|(0<<8)|(1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0)
str r0, [r5, #4]
bl ReadNandID
mov r6, #0
ldr r0, =0xec73
cmp r5, r0
beq %F1
ldr r0, =0xec75
cmp r5, r0
beq %F1
mov r6, #1
1
bl ReadNandStatus
mov r8, #0
ldr r9, =ResetEntry
2
ands r0, r8, #0x1f
bne %F3
mov r0, r8
bl CheckBadBlk
cmp r0, #0
addne r8, r8, #32
bne %F4
3
mov r0, r8
mov r1, r9
bl ReadNandPage
add r9, r9, #512
add r8, r8, #1
4
cmp r8, #512
bcc %B2
mov r5, #NFCONF ;//DsNandFlash
ldr r0, [r5, #4]
bic r0, r0, #1
str r0, [r5, #4]
ldr pc, =copy_proc_beg
;//===========================================================
copy_proc_beg
adr r0, ResetEntry
ldr r2, BaseOfROM
cmp r0, r2
ldreq r0, TopOfROM
beq InitRam
ldr r3, TopOfROM
0
ldmia r0!, {r4-r7}
stmia r2!, {r4-r7}
cmp r2, r3
bcc %B0
sub r2, r2, r3
sub r0, r0, r2
InitRam
ldr r2, BaseOfBSS
ldr r3, BaseOfZero
0
cmp r2, r3
ldrcc r1, [r0], #4
strcc r1, [r2], #4
bcc %B0
mov r0, #0
ldr r3, EndOfBSS
1
cmp r2, r3
strcc r0, [r2], #4
bcc %B1
ldr pc, =%F2 ;//goto compiler address
2
;// [ CLKDIV_VAL>1 ;// means Fclk:Hclk is not 1:1.
;// bl MMU_SetAsyncBusMode
;// |
;// bl MMU_SetFastBusMode ;// default value.
;// ]
;//===========================================================
;// Setup IRQ handler
ldr r0,=HandleIRQ ;//This routine is needed
ldr r1,=IsrIRQ ;//if there isn't' 'subs pc,lr,#4' at 0x18, 0x1c
str r1,[r0]
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