📄 option.h
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/**************************************************************
NAME: option.h
DESC: To measuure the USB download speed, the WDT is used.
To measure up to large time, The WDT interrupt is used.
HISTORY:
Feb.20.2002:Shin, On Pil: Programming start
Mar.25.2002:purnnamu: S3C2400X profile.c is ported for S3C2440X.
**************************************************************/
#ifndef __OPTION_H__
#define __OPTION_H__
#define MEGA (1000000)
//#define FIN (12000000) //hzh
//#define FCLK 271500000 //hzh
//#define FCLK 304000000
//#define FCLK 450000000
//#define FCLK 532000000
#define FIN (16934400)
//#define FCLK 266720000
//#define FCLK 296350000
#define FCLK 399650000
//#define FCLK 530610000
//#define FCLK 533430000
//*** 时钟配置表*** xm
//FIN FCLK MDIV PDIV SDIV
//12.0000MHz 48.00 MHz 56(0X38) 2 2
//12.0000MHz 96.00 MHz 56(0x38) 2 1
//12.0000MHz 271.50 MHz 173(0xad) 2 2
//12.0000MHz 304.00 MHz 68(0x44) 1 1
//12.0000MHz 405.00 MHz 127(0x7f) 2 1
//12.0000MHz 532.00 MHz 125(0x7d) 1 1
//16.9344MHz 47.98 MHz 60(0x3c) 4 2
//16.9344MHz 95.96 MHz 60(0x3c) 4 1
//16.9344MHz 266.72 MHZ 118(0x76) 2 2
//16.9344MHz 296.35 MHZ 97(0x61) 1 2
//16.9344MHz 399.65 MHz 110(0x6e) 3 1
//16.9344MHz 530.61 MHz 86(0x56) 1 1
//16.9344MHz 533.43 MHz 118(0x76) 1 1
//modfied by xm 08/12/28
//#if FIN==12000000 //xm
#if FCLK==271500000
#define MDIV_mpll 173
#define PDIV_mpll 2
#define SDIV_mpll 2
#elif FCLK==304000000
#define MDIV_mpll 68
#define PDIV_mpll 1
#define SDIV_mpll 1
#elif FCLK==405000000
#define MDIV_mpll 127
#define PDIV_mpll 2
#define SDIV_mpll 1
#elif FCLK==532000000
#define MDIV_mpll 125
#define PDIV_mpll 1
#define SDIV_mpll 1
//#endif
//#else //FIN=16.9344MHz
#elif FCLK==266720000
#define MDIV_mpll 118
#define PDIV_mpll 2
#define SDIV_mpll 2
#elif FCLK==296350000
#define MDIV_mpll 97
#define PDIV_mpll 1
#define SDIV_mpll 2
#elif FCLK==399650000
#define MDIV_mpll 110
#define PDIV_mpll 3
#define SDIV_mpll 1
#elif FCLK==530610000
#define MDIV_mpll 86
#define PDIV_mpll 1
#define SDIV_mpll 1
#elif FCLK==533430000
#define MDIV_mpll 118
#define PDIV_mpll 1
#define SDIV_mpll 1
#endif
/*
// Main clock
#if FIN==12000000
#if (FCLK==200000000)
#define HCLK (FCLK/2)
#define PCLK (HCLK/2)
#elif (FCLK==304800000) || (FCLK==271500000) || (FCLK==240000000)
#define HCLK (FCLK/3)
#define PCLK (HCLK/2)
#elif (FCLK==360000000) || (FCLK==380000000) || (FCLK==400000000)
#define HCLK (FCLK/4)
#define PCLK (HCLK/2)
#elif (FCLK==340000000) || (FCLK==350000000) || (FCLK==300000000) || (FCLK==320000000) || (FCLK==330000000)
#define HCLK (FCLK/4)
#define PCLK (HCLK/1)
#endif
#else //FIN=16.9344MHz
#if FCLK==266716800
#define HCLK (FCLK/2)
#define PCLK (HCLK/2)
#elif FCLK==296352000
#define HCLK (FCLK/3)
#define PCLK (HCLK/2)
#elif FCLK==399651840
#define HCLK (FCLK/3)
#define PCLK (HCLK/2)
#endif
#endif
// USB clock
#define UCLK 48000000
*/
//hzh, use variable
#ifdef GLOBAL_CLK
//U32 FCLK;
U32 HCLK;
U32 PCLK;
U32 UCLK;
#else
//extern unsigned int FCLK;
extern unsigned int HCLK;
extern unsigned int PCLK;
extern unsigned int UCLK;
#endif
// BUSWIDTH : 16,32
#define BUSWIDTH (32)
//64MB
// 0x30000000 ~ 0x30ffffff : Download Area (16MB) Cacheable
// 0x31000000 ~ 0x33feffff : Non-Cacheable Area
// 0x33ff0000 ~ 0x33ff47ff : Heap & RW Area
// 0x33ff4800 ~ 0x33ff7fff : FIQ ~ User Stack Area
// 0x33ff8000 ~ 0x33fffeff : Not Useed Area
// 0x33ffff00 ~ 0x33ffffff : Exception & ISR Vector Table
#define _RAM_STARTADDRESS 0x30000000
#define _ISR_STARTADDRESS 0x33ffff00
#define _MMUTT_STARTADDRESS 0x33ff8000
#define _STACK_BASEADDRESS 0x33ff8000
#define HEAPEND 0x33ff0000
#define _NONCACHE_STARTADDRESS 0x31000000
//If you use ADS1.x, please define ADS10
#define ADS10 1
//USB Device Options
#define USBDMA 1 //1->0, hzh
#define USBDMA_DEMAND 0 //the downloadFileSize should be (64*n)
#define BULK_PKT_SIZE 64
// note: makefile,option.a should be changed
#endif /*__OPTION_H__*/
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