count99.vhd

4键矩阵开关

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity count99  is
port (   clk,reset:in std_logic;
      judge2 :in std_logic_vector (3 downto 0);
      judge3 :in std_logic_vector (3 downto 0);
      count1 :out std_logic_vector (3 downto 0);
      count2 :out std_logic_vector (3 downto 0);
      count3 :out std_logic_vector (3 downto 0);
      count4 :out std_logic_vector (3 downto 0));
end count99 ;
architecture aa of count99 is
signal en : std_logic;
signal money : std_logic_vector(7 downto 0);
signal mcount : std_logic_vector (15 downto 0);

begin
money<="00110011"  when ((mcount(15)='1') or (mcount(14)='1') or (mcount(13)='1'))  else "00100010";
en<='0' when judge3="0000" and judge2(3 downto 2)="00" and 
					((judge2(1)='0') or (judge2(1)='1' and judge2(0)='0')) else '1';
process(clk,reset)
variable mm : std_logic_vector (15 downto 0);
begin
if reset='1' then
mm:="0000011100000000";
elsif clk'event and clk='1' then
if en='1' then mm:=mm+money; end if;
if mm(3)='1' and (not(mm(2 downto 1)="00")) then
mm:=mm+6; end if;
if mm(7)='1' and (not(mm(6 downto 5)="00")) then
mm:=mm+"01100000"; end if;
if mm(11)='1' and (not(mm(10 downto 9)="00")) then
mm:=mm+"011000000000"; end if;
end if;

count1<=mm(3 downto 0);
count2<=mm(7 downto 4);
count3<=mm(11 downto 8);
count4<=mm(15 downto 12);
mcount<=mm;

end process;
end aa;