📄 lpc2400.inc
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ADDR4 EQU (AD0_BASE_ADDR + 0x20)
ADDR5 EQU (AD0_BASE_ADDR + 0x24)
ADDR6 EQU (AD0_BASE_ADDR + 0x28)
ADDR7 EQU (AD0_BASE_ADDR + 0x2C)
AD0STAT EQU (AD0_BASE_ADDR + 0x30)
;/********************************************************************************************************
; D/A Converter
;********************************************************************************************************/
DAC_BASE_ADDR EQU 0xE006C000
DACR EQU (DAC_BASE_ADDR + 0x00)
;/********************************************************************************************************
; Watchdog Converter
;********************************************************************************************************/
WDG_BASE_ADDR EQU 0xE0000000
WDMOD EQU (WDG_BASE_ADDR + 0x00)
WDTC EQU (WDG_BASE_ADDR + 0x04)
WDFEED EQU (WDG_BASE_ADDR + 0x08)
WDTV EQU (WDG_BASE_ADDR + 0x0C)
WDCLKSEL EQU (WDG_BASE_ADDR + 0x10)
;/********************************************************************************************************
; CAN CONTROLLERS AND ACCEPTANCE FILTER
;********************************************************************************************************/
CAN_ACCEPT_BASE_ADDR EQU 0xE003C000
CAN_AFMR EQU (CAN_ACCEPT_BASE_ADDR + 0x00)
CAN_SFF_SA EQU (CAN_ACCEPT_BASE_ADDR + 0x04)
CAN_SFF_GRP_SA EQU (CAN_ACCEPT_BASE_ADDR + 0x08)
CAN_EFF_SA EQU (CAN_ACCEPT_BASE_ADDR + 0x0C)
CAN_EFF_GRP_SA EQU (CAN_ACCEPT_BASE_ADDR + 0x10)
CAN_EOT EQU (CAN_ACCEPT_BASE_ADDR + 0x14)
CAN_LUT_ERR_ADR EQU (CAN_ACCEPT_BASE_ADDR + 0x18)
CAN_LUT_ERR EQU (CAN_ACCEPT_BASE_ADDR + 0x1C)
CAN_CENTRAL_BASE_ADDR EQU 0xE0040000
CAN_TX_SR EQU (CAN_CENTRAL_BASE_ADDR + 0x00)
CAN_RX_SR EQU (CAN_CENTRAL_BASE_ADDR + 0x04)
CAN_MSR EQU (CAN_CENTRAL_BASE_ADDR + 0x08)
CAN1_BASE_ADDR EQU 0xE0044000
CAN1MOD EQU (CAN1_BASE_ADDR + 0x00)
CAN1CMR EQU (CAN1_BASE_ADDR + 0x04)
CAN1GSR EQU (CAN1_BASE_ADDR + 0x08)
CAN1ICR EQU (CAN1_BASE_ADDR + 0x0C)
CAN1IER EQU (CAN1_BASE_ADDR + 0x10)
CAN1BTR EQU (CAN1_BASE_ADDR + 0x14)
CAN1EWL EQU (CAN1_BASE_ADDR + 0x18)
CAN1SR EQU (CAN1_BASE_ADDR + 0x1C)
CAN1RFS EQU (CAN1_BASE_ADDR + 0x20)
CAN1RID EQU (CAN1_BASE_ADDR + 0x24)
CAN1RDA EQU (CAN1_BASE_ADDR + 0x28)
CAN1RDB EQU (CAN1_BASE_ADDR + 0x2C)
CAN1TFI1 EQU (CAN1_BASE_ADDR + 0x30)
CAN1TID1 EQU (CAN1_BASE_ADDR + 0x34)
CAN1TDA1 EQU (CAN1_BASE_ADDR + 0x38)
CAN1TDB1 EQU (CAN1_BASE_ADDR + 0x3C)
CAN1TFI2 EQU (CAN1_BASE_ADDR + 0x40)
CAN1TID2 EQU (CAN1_BASE_ADDR + 0x44)
CAN1TDA2 EQU (CAN1_BASE_ADDR + 0x48)
CAN1TDB2 EQU (CAN1_BASE_ADDR + 0x4C)
CAN1TFI3 EQU (CAN1_BASE_ADDR + 0x50)
CAN1TID3 EQU (CAN1_BASE_ADDR + 0x54)
CAN1TDA3 EQU (CAN1_BASE_ADDR + 0x58)
CAN1TDB3 EQU (CAN1_BASE_ADDR + 0x5C)
CAN2_BASE_ADDR EQU 0xE0048000
CAN2MOD EQU (CAN2_BASE_ADDR + 0x00)
CAN2CMR EQU (CAN2_BASE_ADDR + 0x04)
CAN2GSR EQU (CAN2_BASE_ADDR + 0x08)
CAN2ICR EQU (CAN2_BASE_ADDR + 0x0C)
CAN2IER EQU (CAN2_BASE_ADDR + 0x10)
CAN2BTR EQU (CAN2_BASE_ADDR + 0x14)
CAN2EWL EQU (CAN2_BASE_ADDR + 0x18)
CAN2SR EQU (CAN2_BASE_ADDR + 0x1C)
CAN2RFS EQU (CAN2_BASE_ADDR + 0x20)
CAN2RID EQU (CAN2_BASE_ADDR + 0x24)
CAN2RDA EQU (CAN2_BASE_ADDR + 0x28)
CAN2RDB EQU (CAN2_BASE_ADDR + 0x2C)
CAN2TFI1 EQU (CAN2_BASE_ADDR + 0x30)
CAN2TID1 EQU (CAN2_BASE_ADDR + 0x34)
CAN2TDA1 EQU (CAN2_BASE_ADDR + 0x38)
CAN2TDB1 EQU (CAN2_BASE_ADDR + 0x3C)
CAN2TFI2 EQU (CAN2_BASE_ADDR + 0x40)
CAN2TID2 EQU (CAN2_BASE_ADDR + 0x44)
CAN2TDA2 EQU (CAN2_BASE_ADDR + 0x48)
CAN2TDB2 EQU (CAN2_BASE_ADDR + 0x4C)
CAN2TFI3 EQU (CAN2_BASE_ADDR + 0x50)
CAN2TID3 EQU (CAN2_BASE_ADDR + 0x54)
CAN2TDA3 EQU (CAN2_BASE_ADDR + 0x58)
CAN2TDB3 EQU (CAN2_BASE_ADDR + 0x5C)
;/********************************************************************************************************
; MultiMedia Card Interface(MCI) Controller
;********************************************************************************************************/
MCI_BASE_ADDR EQU 0xE008C000
MCIPower EQU (MCI_BASE_ADDR + 0x00)
MCIClock EQU (MCI_BASE_ADDR + 0x04)
MCIArgument EQU (MCI_BASE_ADDR + 0x08)
MCICommand EQU (MCI_BASE_ADDR + 0x0C)
MCIRespCmd EQU (MCI_BASE_ADDR + 0x10)
MCIResponse0 EQU (MCI_BASE_ADDR + 0x14)
MCIResponse1 EQU (MCI_BASE_ADDR + 0x18)
MCIResponse2 EQU (MCI_BASE_ADDR + 0x1C)
MCIResponse3 EQU (MCI_BASE_ADDR + 0x20)
MCIDataTimer EQU (MCI_BASE_ADDR + 0x24)
MCIDataLength EQU (MCI_BASE_ADDR + 0x28)
MCIDataCtrl EQU (MCI_BASE_ADDR + 0x2C)
MCIDataCnt EQU (MCI_BASE_ADDR + 0x30)
MCIStatus EQU (MCI_BASE_ADDR + 0x34)
MCIClear EQU (MCI_BASE_ADDR + 0x38)
MCIMask0 EQU (MCI_BASE_ADDR + 0x3C)
MCIMask1 EQU (MCI_BASE_ADDR + 0x40)
MCIFifoCnt EQU (MCI_BASE_ADDR + 0x48)
MCIFIFO EQU (MCI_BASE_ADDR + 0x80)
;/********************************************************************************************************
; I2S Interface Controller (I2S)
;********************************************************************************************************/
I2S_BASE_ADDR EQU 0xE0088000
I2SDAO EQU (I2S_BASE_ADDR + 0x00)
I2SDAI EQU (I2S_BASE_ADDR + 0x04)
I2STXFIFO EQU (I2S_BASE_ADDR + 0x08)
I2SRXFIFO EQU (I2S_BASE_ADDR + 0x0C)
I2SSTATE EQU (I2S_BASE_ADDR + 0x10)
I2SDMA1 EQU (I2S_BASE_ADDR + 0x14)
I2SDMA2 EQU (I2S_BASE_ADDR + 0x18)
I2SIRQ EQU (I2S_BASE_ADDR + 0x1C)
I2STXRATE EQU (I2S_BASE_ADDR + 0x20)
I2SRXRATE EQU (I2S_BASE_ADDR + 0x24)
;/********************************************************************************************************
; General-purpose DMA Controller
;********************************************************************************************************/
DMA_BASE_ADDR EQU 0xFFE04000
DMACIntStatus EQU (DMA_BASE_ADDR + 0x000)
DMACIntTCStatus EQU (DMA_BASE_ADDR + 0x004)
DMACIntTCClear EQU (DMA_BASE_ADDR + 0x008)
DMACIntErrorStatus EQU (DMA_BASE_ADDR + 0x00C)
DMACIntErrClr EQU (DMA_BASE_ADDR + 0x010)
DMACRawIntTCStatus EQU (DMA_BASE_ADDR + 0x014)
DMACRawIntErrorStatus EQU (DMA_BASE_ADDR + 0x018)
DMACEnbldChns EQU (DMA_BASE_ADDR + 0x01C)
DMACSoftBReq EQU (DMA_BASE_ADDR + 0x020)
DMACSoftSReq EQU (DMA_BASE_ADDR + 0x024)
DMACSoftLBReq EQU (DMA_BASE_ADDR + 0x028)
DMACSoftLSReq EQU (DMA_BASE_ADDR + 0x02C)
DMACConfiguration EQU (DMA_BASE_ADDR + 0x030)
DMACSync EQU (DMA_BASE_ADDR + 0x034)
;/********************************************************************************************************
; DMA channel 0 registers
;********************************************************************************************************/
DMACC0SrcAddr EQU (DMA_BASE_ADDR + 0x100)
DMACC0DestAddr EQU (DMA_BASE_ADDR + 0x104)
DMACC0LLI EQU (DMA_BASE_ADDR + 0x108)
DMACC0Control EQU (DMA_BASE_ADDR + 0x10C)
DMACC0Configuration EQU (DMA_BASE_ADDR + 0x110)
;/********************************************************************************************************
; DMA channel 1 registers
;********************************************************************************************************/
DMACC1SrcAddr EQU (DMA_BASE_ADDR + 0x120)
DMACC1DestAddr EQU (DMA_BASE_ADDR + 0x124)
DMACC1LLI EQU (DMA_BASE_ADDR + 0x128)
DMACC1Control EQU (DMA_BASE_ADDR + 0x12C)
DMACC1Configuration EQU (DMA_BASE_ADDR + 0x130)
;/********************************************************************************************************
; USB Controller
;********************************************************************************************************/
USB_INT_BASE_ADDR EQU 0xE01FC1C0
USB_BASE_ADDR EQU 0xFFE0C200
USBClkCtrl EQU (0xFFE0CFF4)
USBClkSt EQU (0xFFE0CFF8)
USBPortSel EQU (0xFFE0C110)
USBIntSt EQU (USB_INT_BASE_ADDR + 0x00)
;/********************************************************************************************************
; USB Device Interrupt Registers
;********************************************************************************************************/
USBDevIntSt EQU (USB_BASE_ADDR + 0x00)
USBDevIntEn EQU (USB_BASE_ADDR + 0x04)
USBDevIntClr EQU (USB_BASE_ADDR + 0x08)
USBDevIntSet EQU (USB_BASE_ADDR + 0x0C)
USBDevIntPri EQU (USB_BASE_ADDR + 0x2C)
;/********************************************************************************************************
; USB Device Endpoint Interrupt Registers
;********************************************************************************************************/
USBEpIntSt EQU (USB_BASE_ADDR + 0x30)
USBEpIntEn EQU (USB_BASE_ADDR + 0x34)
USBEpIntClr EQU (USB_BASE_ADDR + 0x38)
USBEpIntSet EQU (USB_BASE_ADDR + 0x3C)
USBEpIntPri EQU (USB_BASE_ADDR + 0x40)
;/********************************************************************************************************
; USB Device Endpoint Realization Registers
;********************************************************************************************************/
USBReEp EQU (USB_BASE_ADDR + 0x44)
USBEpInd EQU (USB_BASE_ADDR + 0x48)
USBMaxPSize EQU (USB_BASE_ADDR + 0x4C)
;/********************************************************************************************************
; USB Device Command Reagisters
;********************************************************************************************************/
USBCmdCode EQU (USB_BASE_ADDR + 0x10)
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