i2c.h

WinCE5.0BSP for Renesas SH7770

//
// Copyright(C) Renesas Technology Corp. 2002-2003. All rights reserved.
//
// I2C driver for ITS-DS7
//
// FILE      : I2C.H
// CREATED   : 2002.06.26
// MODIFIED  : 2003.06.20
// AUTHOR    : Renesas Technology Corp.
// HARDWARE  : RENESAS ITS-DS7
// HISTORY   : 
//             2003.06.20
//              - Created release code.
//                (based on I2C driver for ITS-DS4 Ver.1.2.0 for WCE4.2)
//

#ifndef _I2C_H_
#define _I2C_H_

#define I2C_MASTER_TX	0x00000010
#define I2C_MASTER_RX	0x00000020
#define I2C_SLAVE_TX	0x00000040
#define I2C_SLAVE_RX	0x00000080
#define I2C_INTERRUPT	0x00000001

#define I2C_MASTER_MNR	0x00000100
#define I2C_MASTER_MAL	0x00000200
#define I2C_MASTER_MST	0x00000400
#define I2C_SLAVE_SSR	0x00000800

typedef struct _I2C_WORK {
	volatile DWORD	dwType;
	volatile DWORD	dwCount;
	volatile DWORD	dwPoint;
	volatile BYTE	bBuffer[0x800-12];
}I2C_WORK, *PI2C_WORK;


typedef union _SlaveControlRegister {
	struct {
		DWORD	FNA : 1;			// Force Non-Acknowledge
		DWORD	GCAE : 1;			// General Call Acknowledgement Enable
		DWORD	SIE : 1;			// Slave Interface Enable
		DWORD	SDBS : 1;			// Slave Data Buffer Select
		DWORD	Reserved : 28;		// Reserved
	} bits;
	DWORD	AsDWORD;
} RegSCR;
typedef union _SlaveStatusRegister {
	struct {
		DWORD	SAR : 1;			// Slave Address Received
		DWORD	SDR : 1;			// Slave Data Received
		DWORD	SDT : 1;			// Slave Data Transmitted
		DWORD	SDE : 1;			// Slave Data Empty
		DWORD	SSR : 1;			// Slave Stop Received
		DWORD	STM : 1;			// Slave Transmit Mode
		DWORD	GCAR : 1;			// General Call Address Received
		DWORD	Reserved : 25;		// Reserved
	} bits;
	DWORD	AsDWORD;
} RegSSR;
typedef union _SlaveInterruptEnableRegister {
	struct {
		DWORD	SARE : 1;			// Slave Address Received Interrupt Enable
		DWORD	SDRE : 1;			// Slave Data Received Interrupt Enable
		DWORD	SDTE : 1;			// Slave Data Transmitted Interrupt Enable
		DWORD	SDEE : 1;			// Slave Data Empty Interrupt Enable
		DWORD	SSRE : 1;			// Slave Stop Received Interrupt Enable
		DWORD	Reserved : 27;		// Reserved
	} bits;
	DWORD	AsDWORD;
} RegSIER;
typedef union _MasterControlRegister {
	struct {
		DWORD	ESG : 1;			// Enable Start Generation
		DWORD	FSB : 1;			// Force Stop onto the Bus
		DWORD	TSBE : 1;			// Transmission of Start Byte Enbale
		DWORD	MIE : 1;			// Master Interface Enable
		DWORD	OBPC : 1;			// Override Bus Pin Control
		DWORD	FSDA : 1;			// Force SDA
		DWORD	FSCL : 1;			// Force SCL
		DWORD	MDBS : 1;			// Master Data Buffer Select
		DWORD	Reserved : 24;		// Reserved
	} bits;
	DWORD	AsDWORD;
} RegMCR;
typedef union _MasterStatusRegister {
	struct {
		DWORD	MAT : 1;			// Master Address Transmitted
		DWORD	MDR : 1;			// Master Data Received
		DWORD	MDT : 1;			// Master Data Transmitted
		DWORD	MDE : 1;			// Master Data Empty
		DWORD	MST : 1;			// Master Stop Transmitted
		DWORD	MAL : 1;			// Master Arbitration Lost
		DWORD	MNR : 1;			// Master Nack Received
		DWORD	Reserved : 25;		// Reserved
	} bits;
	DWORD	AsDWORD;
} RegMSR;
typedef union _MasterInterruptEnableRegister {
	struct {
		DWORD	MATE : 1;			// Master Address Transmitted Interrupt Enable
		DWORD	MDRE : 1;			// Master Data Received Interrupt Enable
		DWORD	MDTE : 1;			// Master Data Transmitted Interrupt Enable
		DWORD	MDEE : 1;			// Master Data Empty Interrupt Enable
		DWORD	MSTE : 1;			// Master Stop Transmitted Interrupt Enable
		DWORD	MALE : 1;			// Master Arbitration Lost Interrupt Enable
		DWORD	MNRE : 1;			// Master Nack Received Interrupt Enable
		DWORD	Reserved : 25;		// Reserved
	} bits;
	DWORD	AsDWORD;
} RegMIER;
typedef union _ClockControlRegister {
	struct {
		DWORD	CDF : 2;			// Clock Division Factor
		DWORD	SCGD : 6;			// SCL Clock Generation Divider
		DWORD	Reserved : 24;		// Reserved;
	} bits;
	DWORD	AsDWORD;
} RegCCR;

typedef struct _I2C_DRIVER_INFO {
	HANDLE				hIntEvent;
	PVBYTE				pvBaseAddress;

	CRITICAL_SECTION	csI2C;

	PVBYTE				SCR;			// Slave Control Register
	PVBYTE				MCR;			// Master Control Register
	PVBYTE				SSR;			// Slave Status Register
	PVBYTE				MSR;			// Master Status Register
	PVBYTE				SIER;			// Slave Interrupt Enable Register
	PVBYTE				MIER;			// Master Interrupt Enable Register
	PVBYTE				CCR;			// Clock Control Register
	PVBYTE				SAR;			// Slave Address Register
	PVBYTE				MAR;			// Master Addres Register
	PVBYTE				RXD;			// Receive Data Register
	PVBYTE				TXD;			// Transmit Data Register


	PI2C_WORK	data;

} I2C_DRIVER_INFO, *PI2C_DRIVER_INFO;

typedef struct _I2C_OPEN_INFO {
	PI2C_DRIVER_INFO	pI2CHandle;
	DWORD				dwAccess;
	DWORD				dwShareMode;

	DWORD				dwMaster;		// I2C operation mode
	BOOL				bSingleStage;	// Single-Stage buffer select
	DWORD				dwBaudrate;		// Baudrate
} I2C_OPEN_INFO, *PI2C_OPEN_INFO;




#define I2C_WRITE_TIMEOUT			3000		// timeout 100ms
#define I2C_READ_TIMEOUT			3000		// 
#define I2C_SWRITE_TIMEOUT			3000
#define I2C_SREAD_TIMEOUT			3000

#define I2C_SCR_OFFSET		0x00000000
#define I2C_MCR_OFFSET		0x00000004
#define I2C_SSR_OFFSET		0x00000008
#define I2C_MSR_OFFSET		0x0000000C
#define I2C_SIER_OFFSET		0x00000010
#define I2C_MIER_OFFSET		0x00000014
#define I2C_CCR_OFFSET		0x00000018
#define I2C_SAR_OFFSET		0x0000001C
#define I2C_MAR_OFFSET		0x00000020
#define I2C_RXD_OFFSET		0x00000024
#define I2C_TXD_OFFSET		0x00000024


//
DWORD	i2cInterruptThread(VOID);
BOOL	InitializeI2C(PI2C_OPEN_INFO, BOOL);
BOOL	SetCCR(PI2C_OPEN_INFO);
DWORD	I2C_MasterRead(PI2C_OPEN_INFO, LPVOID, DWORD);
DWORD	I2C_SlaveRead(PI2C_OPEN_INFO, LPVOID, DWORD);
DWORD	I2C_MasterWrite(PI2C_OPEN_INFO, LPCVOID, DWORD);
DWORD	I2C_SlaveWrite(PI2C_OPEN_INFO, LPCVOID, DWORD);

#endif	// _I2C_H_