📄 pdsocket.cpp

📁 WinCE5.0BSP for Renesas SH7770
💻 CPP
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	    /* Set 1MB System Memory Windows*/
	    
	    //Set to the Max Value
	    WRITE_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pMW0C1, (MR_SHPC_MW0C1_WINEN | MR_SHPC_MW0C1_WIDTH4 |
	        MR_SHPC_MW0C1_WIDTH3| MR_SHPC_MW0C1_WIDTH2 | MR_SHPC_MW0C1_WIDTH1 | MR_SHPC_MW0C1_WIDTH0 | MR_SHPC_MW0C1_HOLD1 | MR_SHPC_MW0C1_HOLD0 | 
	        MR_SHPC_MW0C1_SETUP0| MR_SHPC_MW0C1_SETUP1 | (USHORT)MEM_WIN0_CNTRL1(v_PcmciaInit[nSlot].attr_win_base))); 

	    // MW1C1: 1MB Common Memory Window
	    //Set to the Max Value
	    WRITE_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pMW1C1, (MR_SHPC_MW1C1_WINEN | MR_SHPC_MW1C1_WIDTH4 |
	         MR_SHPC_MW1C1_WIDTH3 | MR_SHPC_MW1C1_WIDTH2 | MR_SHPC_MW1C1_WIDTH1 | MR_SHPC_MW1C1_WIDTH0 | MR_SHPC_MW1C1_HOLD1 |
	         MR_SHPC_MW1C1_HOLD0 | MR_SHPC_MW1C1_SETUP1 | MR_SHPC_MW1C1_SETUP0 | (USHORT)MEM_WIN1_CNTRL1(v_PcmciaInit[nSlot].cmn_win_base)));


	    //IOWC1: 1MB IO Window
	    //Set to the Max Value
	    WRITE_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pIOWC1,(MR_SHPC_IOWC1_WINEN | MR_SHPC_IOWC1_WIDTH4 |
	        MR_SHPC_IOWC1_WIDTH3 | MR_SHPC_IOWC1_WIDTH2 | MR_SHPC_IOWC1_WIDTH1 | MR_SHPC_IOWC1_WIDTH0| 
	        MR_SHPC_IOWC1_HOLD1 | MR_SHPC_IOWC1_HOLD0 | MR_SHPC_IOWC1_SETUP1 | MR_SHPC_IOWC1_SETUP0 | (USHORT)IO_WIN_CNTRL1(v_PcmciaInit[nSlot].io_win_base)));


	    /* Set 256KB Card Memory Windows*/

	    // MW0C2: 256KB Attribute Memory Window
	    WRITE_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pMW0C2,(MR_SHPC_MW0C2_SWAP | MR_SHPC_MW0C2_SIZE | 
	        MEM_WIN0_CNTRL2(MR_SHPC_MW0C2_CA))));   //16 bit data access

	    // MW1C2: 256KB Common Memory Window
	    WRITE_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pMW1C2,(MR_SHPC_MW1C2_SWAP | MR_SHPC_MW1C2_SIZE | 
	        MR_SHPC_MW1C2_REG | MEM_WIN1_CNTRL2(MR_SHPC_MW1C2_CA))));   //16 bit data access

	    // IOWC2: 256KB IO Memory Window
	    WRITE_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pIOWC2,(MR_SHPC_IOWC2_SWAP | IO_WIN_CNTRL2(MR_SHPC_IOWC2_CA) |
	        MR_SHPC_IOWC2_AUTO_SIZE /*| MR_SHPC_IOWC2_SIZE*/)));    //16 bit data access with auto size


	    /* Set Option Reg.*/
	    WRITE_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pOPT, (MR_SHPC_OPT_LED_OUT_0 | MR_SHPC_OPT_LED_SELECT_BIT2));

	    /* Set Card Control Reg.*/
	    WRITE_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pCCN, 0);  


	    // Set Pulse SysIRQ (INTC is already set to 0) 
	    WRITE_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pINTC, MR_SHPC_INTC_CARD_IRQ);

	    /* PCIC Info Reg.*/
	    READ_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pCIN);
	    
	    // we are in the power off state because neither 5V or 3.3V is asserted at this point.

#ifdef DEBUG
	    PrintRegisters(nSlot);
#endif
	}

    return TRUE;
}

BOOL CPCCardBusBridge::IsCardInserted( int nSlot )
{
    if( ( READ_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pCST) & MR_SHPC_CST_CD_MASK ) == MR_SHPC_CST_CARD_INSERTED )
        return TRUE;
    else
        return FALSE;
}

BOOL CPCCardBusBridge::IsCardReady( int nSlot )
{
    if( READ_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pCST) & MR_SHPC_CST_RDY_BSY )
        return TRUE;
    else 
        return FALSE;
}

UINT8 CPCCardBusBridge::GetVSPinOut( int nSlot )
{
	USHORT mask = (MR_SHPC_CST_VS2 | MR_SHPC_CST_VS1);
    if( ( READ_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pCST) & mask ) == mask )
        return 2; // 5V card
    else 
        return 1; // 3V card
}

DWORD CPCCardBusBridge::GetCardType( int nSlot )
{
    if( READ_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pCCN) & MR_SHPC_CCN_CARD_IO )
    {
        return CFG_IFACE_MEMORY_IO;
    }
    else
    {
        return CFG_IFACE_MEMORY;
    }
}

void CPCCardBusBridge::SetCardType( int nSlot, DWORD dwInterface )
{
    if( dwInterface == CFG_IFACE_MEMORY_IO )
    {
        WRITE_REGISTER_USHORT( m_rgPcmciaRegisters[nSlot].pCCN,
             READ_REGISTER_USHORT( m_rgPcmciaRegisters[nSlot].pCCN ) | MR_SHPC_CCN_CARD_IO );
    }
    else
    {
        WRITE_REGISTER_USHORT( m_rgPcmciaRegisters[nSlot].pCCN,
             READ_REGISTER_USHORT( m_rgPcmciaRegisters[nSlot].pCCN ) & ~MR_SHPC_CCN_CARD_IO );
    }
}

void CPCCardBusBridge::EnableCSCInterrupts( BOOL bEnable )
{
    USHORT bMask = ~( MR_SHPC_INTC_DETECT_ENABLE |MR_SHPC_INTC_RING_IRQ_MASK |MR_SHPC_INTC_CP_ENABLE |
				MR_SHPC_INTC_RDY_ENABLE |MR_SHPC_INTC_BAT_WARN_ENABLE |MR_SHPC_INTC_BAT_DEAD_ENABLE |MR_SHPC_INTC_MGT_IRQ_MASK);
    USHORT bFlag = 0;
    if( bEnable )
    {
        bFlag = (MR_SHPC_INTC_DETECT_ENABLE |MR_SHPC_INTC_RING_IRQ |MR_SHPC_INTC_CP_ENABLE |
				MR_SHPC_INTC_RDY_ENABLE |MR_SHPC_INTC_BAT_WARN_ENABLE |MR_SHPC_INTC_BAT_DEAD_ENABLE |MR_SHPC_INTC_MGT_IRQ);
    }

    DEBUGMSG(ZONE_PDD, (TEXT("+EnableCSCInterrupts INTC:0x%04x\r\n"), bFlag));

    WRITE_REGISTER_USHORT( m_rgPcmciaRegisters[0].pINTC,
                            ( READ_REGISTER_USHORT( m_rgPcmciaRegisters[0].pINTC ) & bMask ) | bFlag );
    WRITE_REGISTER_USHORT( m_rgPcmciaRegisters[1].pINTC,
                            ( READ_REGISTER_USHORT( m_rgPcmciaRegisters[1].pINTC ) & bMask ) | bFlag );
}

void CPCCardBusBridge::EnableClientInterrupt( int nSlot, BOOL bEnable )
{
    USHORT bMask = ~MR_SHPC_INTC_CARD_IRQ_MASK;
    USHORT bFlag = bEnable ? MR_SHPC_INTC_CARD_IRQ : 0;

    DEBUGMSG(ZONE_PDD, (TEXT("+EnableClientInterrupt INTC:0x%04x\r\n"), bFlag));
    WRITE_REGISTER_USHORT( m_rgPcmciaRegisters[nSlot].pINTC,
                           ( READ_REGISTER_USHORT( m_rgPcmciaRegisters[nSlot].pINTC ) & bMask ) | bFlag );
}

#define GR_BAD_VCC   0x0c
#define GR_BAD_VPP   0x03
BOOL    CPCCardBusBridge::ApplyReset( int nSlot,BOOL fReset )
{
    if (fReset)
        WRITE_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pCPWC,
            (READ_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pCPWC) & ~MR_SHPC_CPWC_CARD_RESET));
    else
        WRITE_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pCPWC,
            (READ_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pCPWC) | MR_SHPC_CPWC_CARD_RESET));
    return fReset;

}
BOOL    CPCCardBusBridge::ApplyEnable(int nSlot, BOOL fEnable )
{
    //first lets turn off the buffers that transmit data through to the PCMCIA slots
    // Tri state the outputs 
    if (fEnable)
	    WRITE_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pCPWC,
	        (READ_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pCPWC) | MR_SHPC_CPWC_CARD_ENABLE));
    else
	    WRITE_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pCPWC,
	        (READ_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pCPWC) & ~MR_SHPC_CPWC_CARD_ENABLE));
    return fEnable;

}

BOOL CPCCardBusBridge::ApplyPower(  int nSlot, DWORD dwVccPowerLevel, DWORD dwVppPowerLevel )
{
    DEBUGMSG(ZONE_PDD, (TEXT("+SetPower\r\n")));

    DEBUGCHK( dwVccPowerLevel < PCMCIA_POWER_ENTRIES );
    DEBUGCHK( dwVppPowerLevel < PCMCIA_POWER_ENTRIES );

    DWORD dwPower = cs_rgrgPowerSetting[nSlot][dwVccPowerLevel][dwVppPowerLevel].bValid;
    if( !( dwPower != GR_BAD_VCC || dwPower == GR_BAD_VPP ) )
    {
        return FALSE;
    }

    // Apply power

#ifdef DEBUG
    PrintRegisters(nSlot);
#endif

    POWER_REGISTER_VALUES PowerValues = cs_rgrgPowerSetting[nSlot][dwVccPowerLevel][dwVppPowerLevel];


    // Set VCC and VPP on PCMCIA slots 0 and 1 to original values before power down.

    WRITE_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pCPWC,
        ((READ_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pCPWC) & 0xFFE0) | (PowerValues.CardPowerReg | MR_SHPC_CPWC_VCC_POWER)));
    DEBUGMSG(ZONE_PDD, (TEXT("SetPower slot:%d vcc:%d vpp:%d cardpower:0x%04x => CPWC:0x%08x\r\n"),nSlot, dwVccPowerLevel, dwVppPowerLevel, PowerValues.CardPowerReg, READ_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pCPWC)));

    if (dwVccPowerLevel == 0 && dwVppPowerLevel == 0 ) {
        ApplyEnable(nSlot,FALSE); 
    }

    if( PowerValues.CardPowerReg == 0)
        WRITE_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pCPWC,0 );

#ifdef DEBUG
    PrintRegisters(nSlot);
#endif

    DEBUGMSG(ZONE_PDD, (TEXT("-SetPower\r\n")));
    return TRUE;
}

#ifdef DEBUG
void CPCCardBusBridge::PrintRegisters(int nSlot)
{
    DEBUGMSG(ZONE_PDD, (TEXT("&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&\r\n")));
    DEBUGMSG(ZONE_PDD, (TEXT("& %dMOD  (0x%08x)     0x%04X\r\n"), nSlot, v_PcmciaInit[nSlot].reg_base+MR_SHPC_MOD_OFFSET,   READ_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pMOD)));
    DEBUGMSG(ZONE_PDD, (TEXT("& %dOPT  (0x%08x)     0x%04X\r\n"), nSlot, v_PcmciaInit[nSlot].reg_base+MR_SHPC_OPT_OFFSET,   READ_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pOPT)));
    DEBUGMSG(ZONE_PDD, (TEXT("& %dCST  (0x%08x)     0x%04X\r\n"), nSlot, v_PcmciaInit[nSlot].reg_base+MR_SHPC_CST_OFFSET,   READ_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pCST)));
    DEBUGMSG(ZONE_PDD, (TEXT("& %dINTC (0x%08x)     0x%04X\r\n"), nSlot, v_PcmciaInit[nSlot].reg_base+MR_SHPC_INTC_OFFSET,   READ_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pINTC)));
    DEBUGMSG(ZONE_PDD, (TEXT("& %dCPWC (0x%08x)     0x%04X\r\n"), nSlot, v_PcmciaInit[nSlot].reg_base+MR_SHPC_CPWC_OFFSET,   READ_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pCPWC)));
    DEBUGMSG(ZONE_PDD, (TEXT("& %dMW0C1(0x%08x)     0x%04X\r\n"), nSlot, v_PcmciaInit[nSlot].reg_base+MR_SHPC_MW0C1_OFFSET,   READ_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pMW0C1)));
    DEBUGMSG(ZONE_PDD, (TEXT("& %dMW1C1(0x%08x)     0x%04X\r\n"), nSlot, v_PcmciaInit[nSlot].reg_base+MR_SHPC_MW1C1_OFFSET,   READ_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pMW1C1)));
    DEBUGMSG(ZONE_PDD, (TEXT("& %dIOWC1(0x%08x)     0x%04X\r\n"), nSlot, v_PcmciaInit[nSlot].reg_base+MR_SHPC_IOWC1_OFFSET,   READ_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pIOWC1)));
    DEBUGMSG(ZONE_PDD, (TEXT("& %dMW0C2(0x%08x)     0x%04X\r\n"), nSlot, v_PcmciaInit[nSlot].reg_base+MR_SHPC_MW0C2_OFFSET,   READ_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pMW0C2)));
    DEBUGMSG(ZONE_PDD, (TEXT("& %dMW1C2(0x%08x)     0x%04X\r\n"), nSlot, v_PcmciaInit[nSlot].reg_base+MR_SHPC_MW1C2_OFFSET,   READ_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pMW1C2)));
    DEBUGMSG(ZONE_PDD, (TEXT("& %dIOWC2(0x%08x)     0x%04X\r\n"), nSlot, v_PcmciaInit[nSlot].reg_base+MR_SHPC_IOWC2_OFFSET,   READ_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pIOWC2)));
    DEBUGMSG(ZONE_PDD, (TEXT("& %dCCN  (0x%08x)     0x%04X\r\n"), nSlot, v_PcmciaInit[nSlot].reg_base+MR_SHPC_CCN_OFFSET,   READ_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pCCN)));
	DEBUGMSG(ZONE_PDD, (TEXT("& %dCIN  (0x%08x)     0x%04X\r\n"), nSlot, v_PcmciaInit[nSlot].reg_base+MR_SHPC_CIN_OFFSET,   READ_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pCIN)));
    DEBUGMSG(ZONE_PDD, (TEXT("&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&\r\n")));
}
#endif

BOOL CPCCardBusBridge::IsValidPowerSetting( DWORD dwVcc, DWORD dwVpp )
{
    // since both sockets have the same power requirements, we will use
    // socket 0 data for power validation
    if( cs_rgrgPowerSetting[0][dwVcc][dwVpp].bValid != GR_BAD_VCC )
        return TRUE;
    else
        return FALSE;
}

//------------------------------------------------------------------------------

const SS_POWER_ENTRY CPCCardBusBridge::cs_rgPowerEntries[PCMCIA_POWER_ENTRIES] =
{
    { 0,    PWR_SUPPLY_VCC | PWR_SUPPLY_VPP1 | PWR_SUPPLY_VPP2 },
    { 33,   PWR_SUPPLY_VCC | PWR_SUPPLY_VPP1 | PWR_SUPPLY_VPP2 },
    { 50,   PWR_SUPPLY_VCC | PWR_SUPPLY_VPP1 | PWR_SUPPLY_VPP2 },
    { 120,  PWR_SUPPLY_VPP1 | PWR_SUPPLY_VPP2 },
};

// for TPS2206
const POWER_REGISTER_VALUES CPCCardBusBridge::cs_rgrgPowerSetting[NUM_SLOTS][NUM_POWER_ENTRIES][NUM_POWER_ENTRIES] = {
   {/* this is socket 0 */
   {{TRUE, MR_SHPC_CPWC_VCC_0V | MR_SHPC_CPWC_VPP0V},           // 00 Vcc 0V,   Vpp 0V
    {BAD_VPP, MR_SHPC_CPWC_BAD_VPP },                           // 01 Vcc 0V,   Vpp 3.3V
    {BAD_VPP, MR_SHPC_CPWC_BAD_VPP },                           // 02 Vcc 0V,   Vpp 5V
    {BAD_VPP, MR_SHPC_CPWC_BAD_VPP }},                          // 03 Vcc 0V,   Vpp 12V
   {{TRUE, MR_SHPC_CPWC_VCC_3V | MR_SHPC_CPWC_VPP0V},           // 04 Vcc 3.3V, Vpp 0V
    {TRUE, MR_SHPC_CPWC_VCC_3V | MR_SHPC_CPWC_VPP_EQL_VCC},     // 05 Vcc 3.3V, Vpp 3.3V
    {BAD_VPP, MR_SHPC_CPWC_BAD_VPP },                           // 06 Vcc 3.3V, Vpp 5V
    {TRUE, MR_SHPC_CPWC_VCC_3V | MR_SHPC_CPWC_VPP12V}},         // 07 Vcc 3.3V, Vpp 12V
   {{TRUE, MR_SHPC_CPWC_VCC_5V | MR_SHPC_CPWC_VPP0V},           // 08 Vcc 5V,   Vpp 0V
    {BAD_VPP, MR_SHPC_CPWC_BAD_VPP},                            // 09 Vcc 5V,   Vpp 3.3V
    {TRUE, MR_SHPC_CPWC_VCC_5V | MR_SHPC_CPWC_VPP_EQL_VCC},     // 10 Vcc 5V,   Vpp 5V
    {TRUE, MR_SHPC_CPWC_VCC_5V | MR_SHPC_CPWC_VPP12V}},         // 11 Vcc 5V,   Vpp 12V
   {{BAD_VCC, MR_SHPC_CPWC_BAD_VCC },                           // 12 Vcc 12V,  Vpp 0V
    {BAD_VCC, MR_SHPC_CPWC_BAD_VCC },                           // 13 Vcc 12V,  Vpp 3.3V
    {BAD_VCC, MR_SHPC_CPWC_BAD_VCC },                           // 14 Vcc 12V,  Vpp 5V
    {BAD_VCC, MR_SHPC_CPWC_BAD_VCC }}                           // 15 Vcc 12V,  Vpp 12V
   },
   {/* this is socket 1 */
   {{TRUE, MR_SHPC_CPWC_VCC_0V | MR_SHPC_CPWC_VPP0V},           // 00 Vcc 0V,   Vpp 0V
    {BAD_VPP, MR_SHPC_CPWC_BAD_VPP },                           // 01 Vcc 0V,   Vpp 3.3V
    {BAD_VPP, MR_SHPC_CPWC_BAD_VPP },                           // 02 Vcc 0V,   Vpp 5V
    {BAD_VPP, MR_SHPC_CPWC_BAD_VPP }},                          // 03 Vcc 0V,   Vpp 12V
   {{TRUE, MR_SHPC_CPWC_VCC_3V | MR_SHPC_CPWC_VPP0V},           // 04 Vcc 3.3V, Vpp 0V
    {TRUE, MR_SHPC_CPWC_VCC_3V | MR_SHPC_CPWC_VPP_EQL_VCC},     // 05 Vcc 3.3V, Vpp 3.3V
    {BAD_VPP, MR_SHPC_CPWC_BAD_VPP },                           // 06 Vcc 3.3V, Vpp 5V
    {TRUE, MR_SHPC_CPWC_VCC_3V | MR_SHPC_CPWC_VPP12V}},         // 07 Vcc 3.3V, Vpp 12V
   {{TRUE, MR_SHPC_CPWC_VCC_5V | MR_SHPC_CPWC_VPP0V},           // 08 Vcc 5V,   Vpp 0V
    {BAD_VPP, MR_SHPC_CPWC_BAD_VPP},                            // 09 Vcc 5V,   Vpp 3.3V
    {TRUE, MR_SHPC_CPWC_VCC_5V | MR_SHPC_CPWC_VPP_EQL_VCC},     // 10 Vcc 5V,   Vpp 5V
    {TRUE, MR_SHPC_CPWC_VCC_5V | MR_SHPC_CPWC_VPP12V}},         // 11 Vcc 5V,   Vpp 12V
   {{BAD_VCC, MR_SHPC_CPWC_BAD_VCC },                           // 12 Vcc 12V,  Vpp 0V
    {BAD_VCC, MR_SHPC_CPWC_BAD_VCC },                           // 13 Vcc 12V,  Vpp 3.3V
    {BAD_VCC, MR_SHPC_CPWC_BAD_VCC },                           // 14 Vcc 12V,  Vpp 5V
    {BAD_VCC, MR_SHPC_CPWC_BAD_VCC }}                           // 15 Vcc 12V,  Vpp 12V
   }
};

//------------------------------------------------------------------------------

// this function will be used to create a new instance of the bridge class
CPCCardBusBridge* CreatePCCardBusBridge( LPCTSTR pwszInfo )
{
    return new CPCCardBusBridge( pwszInfo );
}

BOOL CPCCardBusBridge::EnableWindow( int nSlot )
{
	// set window enable so that it is cleared in card exclusion and adding
    WRITE_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pMW0C1, 
        ((READ_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pMW0C1) | MR_SHPC_MW0C1_WINEN)));
    WRITE_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pMW1C1, 
        ((READ_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pMW1C1) | MR_SHPC_MW1C1_WINEN)));
    WRITE_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pIOWC1, 
        ((READ_REGISTER_USHORT(m_rgPcmciaRegisters[nSlot].pIOWC1) | MR_SHPC_IOWC1_WINEN)));
	return TRUE;
}
上一页 1 23
💿 文件大小 922 K
👤 上传用户 reed2453
📂 所属分类 Windows CE
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#Renesas #WinCE #7770 #5.0
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