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📄 hac.c

📁 WinCE5.0BSP for Renesas SH7770
💻 C
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		Loop_n++;
		if(Loop_n > 500){
			DEBUGMSG(ZONE_ERROR, (TEXT("Error! Audio CODEC not ready! \r\n")));
			goto error_ret4;
		}
		if ( Wait_Status((ULONG)0x00026000) == FALSE ) goto error_ret4;
		CSDR_VALUE = (ULONG)READ_REGISTER_ULONG((PULONG)pHAC_CSDR);
	}

	DEBUGMSG(ZONE_INIT, (TEXT("ADC DAC ANL Ready!!\r\n")));
	DEBUGMSG(ZONE_TEST, (TEXT("Loop no = %08x\r\n"), (ULONG)Loop_n));

	WRITE_REGISTER_ULONG((PULONG)pHAC_TSR, (ULONG)(READ_REGISTER_ULONG(pHAC_TSR) & ~(HAC_TSR_CMDAMT|HAC_TSR_CMDDMT)));


	// VRA(Variable Rate Audio) set
	if (Write_codec( (ULONG)0x0002A000, (ULONG)0x00000010 ) == FALSE)	// Set Variable Rate Enable
		goto error_ret4;

	// CODEC parameters
	ulCurrentPlaySamplingRate = 44100 << 4;
	ulCurrentRecSamplingRate = 44100 << 4;
	ulMasterVol = 0x0000 << 4;	// Full Volume
	ulPCMoutVol = 0x0404 << 4;
	ulRecGain   = 0x0606 << 4;
	ulRecSel    = 0x0000 << 4;	// Mic (default)
	ulMicVol    = 0x0008 << 4;	// Mic mixing volume
//	ulLineInVol = 0x8000 << 4;	// Line in mixing volume - mute
	ulLineInVol = 0x0808 << 4;	// Line in mixing volume

#if AC97_USE_MIC == 1
	ulRecSel = 0x0000 << 4; // Mic
#endif
#if AC97_USE_LINE_IN == 1
	ulRecSel = 0x0404 << 4; // Line In 
#endif

	if (Write_codec( (ULONG)0x00002000, (ULONG)ulMasterVol ) == FALSE)	// Set Master Volume
		goto error_ret4;

	if (Write_codec( (ULONG)0x00018000, (ULONG)ulPCMoutVol ) == FALSE)	// Set PCM Out Volume
		goto error_ret4;

	if (Write_codec( (ULONG)0x00032000, (ULONG)ulCurrentRecSamplingRate ) == FALSE)		// Set ADC Sample rate
		goto error_ret4;

	if (Write_codec( (ULONG)0x0002C000, (ULONG)ulCurrentPlaySamplingRate ) == FALSE)	// Set DAC Sample rate
		goto error_ret4;

	if (Write_codec( (ULONG)0x0000A000, (ULONG)0x00080000 ) == FALSE)	// Set BEEP
		goto error_ret4;

	//Audio in set up  start
	if (Write_codec( (ULONG)0x0001C000, (ULONG)ulRecGain ) == FALSE)	// Set DAC Sample rate
		goto error_ret4;

	if (Write_codec( (ULONG)0x0001A000, (ULONG)ulRecSel ) == FALSE)		// Set Record Select
		goto error_ret4;

	if (Write_codec( (ULONG)0x0000E000, (ULONG)ulMicVol ) == FALSE)		// Set Mic Volume
		goto error_ret4;

	if (Write_codec( (ULONG)0x00010000, (ULONG)ulLineInVol ) == FALSE)	// Set Line In Volume
		goto error_ret4;

	//Audio in set up end

	if ( Wait_Status((ULONG)0x00002000) == FALSE ) goto error_ret4;
	DEBUGMSG(ZONE_TEST, (TEXT("Master Vol =%08x\r\n"), (ULONG)READ_REGISTER_ULONG((PULONG)pHAC_CSDR )));
	if ( Wait_Status((ULONG)0x00018000) == FALSE ) goto error_ret4;
	DEBUGMSG(ZONE_TEST, (TEXT("PCM    Vol =%08x\r\n"), (ULONG)READ_REGISTER_ULONG((PULONG)pHAC_CSDR )));
	if ( Wait_Status((ULONG)0x0002A000) == FALSE ) goto error_ret4;
	DEBUGMSG(ZONE_TEST, (TEXT("VRA        =%08x\r\n"), (ULONG)READ_REGISTER_ULONG((PULONG)pHAC_CSDR )));
	if ( Wait_Status((ULONG)0x00032000) == FALSE ) goto error_ret4;
	DEBUGMSG(ZONE_TEST, (TEXT("ADC rate   =%08x\r\n"), (ULONG)READ_REGISTER_ULONG((PULONG)pHAC_CSDR )));
	if ( Wait_Status((ULONG)0x0002C000) == FALSE ) goto error_ret4;
	DEBUGMSG(ZONE_TEST, (TEXT("DAC rate   =%08x\r\n"), (ULONG)READ_REGISTER_ULONG((PULONG)pHAC_CSDR )));
	if ( Wait_Status((ULONG)0x0000E000) == FALSE ) goto error_ret4;
	DEBUGMSG(ZONE_TEST, (TEXT("Mic    Vol =%08x\r\n"), (ULONG)READ_REGISTER_ULONG((PULONG)pHAC_CSDR )));

	//DQR_En
	if ( Wait_Status((ULONG)0x0007c000) == FALSE ) goto error_ret4;
	REG_VALUE = (ULONG)READ_REGISTER_ULONG((PULONG)pHAC_CSDR );

	return	TRUE;

error_ret4:
	if(Loop_r < AC97_RETRTY_MAX) goto reset_codec;
	RETAILMSG(1, (TEXT("AC97: Init Error!\r\n")));
	return	FALSE;
}


/*****************************************************************************
*   FUNCTION :  	module_txdmastart
*   DESCRIPTION :	HAC Tx Start
*   INPUTS :		None
*   OUTPUTS :     	None
*   DESIGN NOTES :  
*   CAUTIONS :		
*****************************************************************************/
VOID
module_txdmastart(
   VOID
   )
{
	ULONG	RegValue;

	FUNC_WPDD("+hac_txdmastart");

	RegValue  = READ_REGISTER_ULONG((PULONG)pHAC_ACR);
    RegValue |= (ULONG)(HAC_ACR_TX12_ATOMIC | HAC_ACR_DMATX16);
	WRITE_REGISTER_ULONG((PULONG)pHAC_ACR, (ULONG)RegValue );

	FUNC_WPDD("-hac_txdmastart");
}


/*****************************************************************************
*   FUNCTION :  	module_txstop
*   DESCRIPTION :	HAC Tx Stop
*   INPUTS :		None
*   OUTPUTS :     	None
*   DESIGN NOTES :  
*   CAUTIONS :		
*****************************************************************************/
VOID
module_txstop(
   VOID
   )
{
	FUNC_WPDD("+hac_txstop");

	WRITE_REGISTER_ULONG((PULONG)pHAC_ACR,
			(READ_REGISTER_ULONG((PULONG)pHAC_ACR) & ~(ULONG)(HAC_ACR_DMATX16)) |
								  (ULONG)HAC_ACR_TX12_ATOMIC );

	FUNC_WPDD("-hac_txstop");
}


/*****************************************************************************
*   FUNCTION :  	module_rxdmastart
*   DESCRIPTION :	HAC Rx Start
*   INPUTS :		None
*   OUTPUTS :     	None
*   DESIGN NOTES :  
*   CAUTIONS :		
*****************************************************************************/
VOID
module_rxdmastart(
   VOID
   )
{
	ULONG	RegValue;

	FUNC_WPDD("+hac_rxdmastart");

	RegValue  = READ_REGISTER_ULONG((PULONG)pHAC_ACR);
	RegValue |= (ULONG)(HAC_ACR_TX12_ATOMIC | HAC_ACR_DMARX16);
	WRITE_REGISTER_ULONG((PULONG)pHAC_ACR, (ULONG)RegValue );

	FUNC_WPDD("-hac_rxdmastart");
}


/*****************************************************************************
*   FUNCTION :  	module_rxstop
*   DESCRIPTION :	HAC Rx Stop
*   INPUTS :		None
*   OUTPUTS :     	None
*   DESIGN NOTES :  
*   CAUTIONS :		
*****************************************************************************/
VOID
module_rxstop(
   VOID
   )
{
	FUNC_WPDD("+hac_rxstop");

	WRITE_REGISTER_ULONG((PULONG)pHAC_ACR,
			(READ_REGISTER_ULONG((PULONG)pHAC_ACR) & ~(ULONG)(HAC_ACR_DMARX16)) |
								  (ULONG)HAC_ACR_TX12_ATOMIC );

	FUNC_WPDD("-hac_rxstop");
}


/*****************************************************************************
*   FUNCTION :  	module_txstart
*   DESCRIPTION :	HAC Tx Start
*   INPUTS :		None
*   OUTPUTS :     	None
*   DESIGN NOTES :  
*   CAUTIONS :		
*****************************************************************************/
VOID
module_txstart(
   VOID
   )
{
	FUNC_WPDD("+hac_txstart");

	WRITE_REGISTER_ULONG((PULONG)pHAC_CR, HAC_CR_ST|HAC_CR_RESERVE);
	WRITE_REGISTER_ULONG((PULONG)pHAC_ACR,
			(READ_REGISTER_ULONG((PULONG)pHAC_ACR) | (ULONG)HAC_ACR_TX12_ATOMIC) );	// ATOMIC Enable

	FUNC_WPDD("-hac_txstart");
}


/*****************************************************************************
*   FUNCTION :  	module_rxstart
*   DESCRIPTION :	HAC Rx Start
*   INPUTS :		None
*   OUTPUTS :     	None
*   DESIGN NOTES :  
*   CAUTIONS :		
*****************************************************************************/
VOID
module_rxstart(
   VOID
   )
{
	FUNC_WPDD("+hac_rxstart");

	WRITE_REGISTER_ULONG((PULONG)pHAC_CR, HAC_CR_ST|HAC_CR_RESERVE);
	WRITE_REGISTER_ULONG((PULONG)pHAC_ACR,
			(READ_REGISTER_ULONG((PULONG)pHAC_ACR) | (ULONG)HAC_ACR_TX12_ATOMIC) );	// ATOMIC Enable

	FUNC_WPDD("-hac_rxstart");
}


/*****************************************************************************
*   FUNCTION :  	Wait_CSAR
*   DESCRIPTION :   wait for CSAR register empty
*   INPUTS :		None
*   OUTPUTS :     	None
*   DESIGN NOTES :
*   CAUTIONS :		
*****************************************************************************/
BOOL Wait_CSAR(void)
{
	DWORD	i;

	i = 0;
	while(( READ_REGISTER_ULONG((PULONG)pHAC_TSR ) & HAC_TSR_CMDAMT ) != HAC_TSR_CMDAMT)
	{
		BusyWait(AdjustMicroSecondsToLoopCount( 21 ));	// wait 21us
		i++;
		if ( i > 10000 ){
			DEBUGMSG(ZONE_ERROR, (TEXT("AC97:Time out error in Wait_CSAR !\r\n")));
			return FALSE;
		}
	}
	WRITE_REGISTER_ULONG((PULONG)pHAC_TSR, (ULONG)(READ_REGISTER_ULONG(pHAC_TSR) & ~HAC_TSR_CMDAMT));
	return TRUE;
}

/*****************************************************************************
*   FUNCTION :  	Wait_CSDR
*   DESCRIPTION :   wait for CSDR register empty
*   INPUTS :		None
*   OUTPUTS :     	None
*   DESIGN NOTES :
*   CAUTIONS :		
*****************************************************************************/
BOOL Wait_CSDR(void)
{
	DWORD	i;

	i = 0;
	while(( (ULONG)READ_REGISTER_ULONG((PULONG)pHAC_TSR ) & HAC_TSR_CMDDMT ) != HAC_TSR_CMDDMT)
	{
		BusyWait(AdjustMicroSecondsToLoopCount( 21 ));	// wait 21us
		i++;
		if ( i > 10000 ){
			DEBUGMSG(ZONE_ERROR, (TEXT("AC97:Time out error in Wait_CSDR !\r\n")));
			return FALSE;
		}
	}

	WRITE_REGISTER_ULONG((PULONG)pHAC_TSR, (ULONG)(READ_REGISTER_ULONG(pHAC_TSR) & ~HAC_TSR_CMDDMT));
	return TRUE;
}


/*****************************************************************************
*   FUNCTION :  	Wait_AddrRdy
*   DESCRIPTION :   wait for Status Address Ready
*   INPUTS :		None
*   OUTPUTS :     	None
*   DESIGN NOTES :
*   CAUTIONS :		
*****************************************************************************/
BOOL Wait_AddrRdy(void)
{
	DWORD	i;

	i = 0;
	while(( (ULONG)READ_REGISTER_ULONG((PULONG)pHAC_RSR ) & HAC_RSR_STARY ) != HAC_RSR_STARY)
	{
		BusyWait(AdjustMicroSecondsToLoopCount( 21 ));	// wait 21us
		i++;
		if ( i > 10000 ){
			DEBUGMSG(ZONE_ERROR, (TEXT("AC97:Time out error in Wait_AddrRdy !\r\n")));
			return FALSE;
		}
	}

	WRITE_REGISTER_ULONG((PULONG)pHAC_RSR, READ_REGISTER_ULONG(pHAC_RSR) & ~HAC_RSR_STARY );
	return TRUE;
}

/*****************************************************************************
*   FUNCTION :  	Wait_DataRdy
*   DESCRIPTION :   wait for Status Data Ready
*   INPUTS :		None
*   OUTPUTS :     	None
*   DESIGN NOTES :
*   CAUTIONS :		
*****************************************************************************/
BOOL Wait_DataRdy(void)
{
	DWORD	i;

	i = 0;
	while(( (ULONG)READ_REGISTER_ULONG((PULONG)pHAC_RSR ) & HAC_RSR_STDRY ) != HAC_RSR_STDRY)
	{
		BusyWait(AdjustMicroSecondsToLoopCount( 21 ));	// wait 21us
		i++;
		if ( i > 10000 ){
			DEBUGMSG(ZONE_ERROR, (TEXT("AC97:Time out error in Wait_DataRdy !\r\n")));
			return FALSE;
		}
	}

	WRITE_REGISTER_ULONG((PULONG)pHAC_RSR, READ_REGISTER_ULONG(pHAC_RSR) & ~HAC_RSR_STDRY );
	return TRUE;
}

/*****************************************************************************
*   FUNCTION :  	Wait_Status
*   DESCRIPTION :   wait for Status data
*   INPUTS :		CODEC register address 
*   OUTPUTS :     	None
*   DESIGN NOTES :
*   CAUTIONS :		
*****************************************************************************/
BOOL Wait_Status(
	ULONG RegAddr
	)
{
	DWORD	i;
	ULONG	CSAR_VALUE;

	i = 0;
	WRITE_REGISTER_ULONG( (PULONG)pHAC_RSR, (ULONG)0x00000000 );
	WRITE_REGISTER_ULONG( (PULONG)pHAC_CSAR, (ULONG)RegAddr | 0x00080000 );

	BusyWait(AdjustMicroSecondsToLoopCount( 1 ));		// wait 1us
	WRITE_REGISTER_ULONG( (PULONG)pHAC_CSAR, (ULONG)RegAddr | 0x00080000 );

	if ( Wait_CSAR() == FALSE ) return FALSE;

	if ( Wait_AddrRdy() == FALSE ) return FALSE;
	CSAR_VALUE = (ULONG)( READ_REGISTER_ULONG((PULONG)pHAC_CSAR) & 0x0007F000 );
	while ( CSAR_VALUE != RegAddr ){
		BusyWait(AdjustMicroSecondsToLoopCount( 21 ));	// wait 21us
		i++;
		if ( i > 10000 ){
			DEBUGMSG(ZONE_ERROR, (TEXT("AC97:Time out error in Wait_Status(%08x) !\r\n"), CSAR_VALUE ));
			return FALSE;
		}
		if ( Wait_AddrRdy() == FALSE ) return FALSE;
		CSAR_VALUE = (ULONG)( READ_REGISTER_ULONG((PULONG)pHAC_CSAR) & 0x0007F000 );
	}

	if ( Wait_DataRdy() == FALSE ) return FALSE;

	return TRUE;
}


/*****************************************************************************
*   FUNCTION :  	Write_codec
*   DESCRIPTION :   wait for Status data
*   INPUTS :		CODEC register address and data
*   OUTPUTS :     	None
*   DESIGN NOTES :
*   CAUTIONS :		
*****************************************************************************/
BOOL Write_codec(
	ULONG RegAddr,
	ULONG RegData
	)
{
	DWORD	i;

	i = 0;
Retry:

	if ( READ_REGISTER_ULONG(pHAC_TSR) & HAC_TSR_CMDDMT )
		WRITE_REGISTER_ULONG((PULONG)pHAC_TSR, (ULONG)(READ_REGISTER_ULONG(pHAC_TSR) & ~HAC_TSR_CMDDMT));
		
	if ( READ_REGISTER_ULONG(pHAC_TSR) & HAC_TSR_CMDAMT )
		WRITE_REGISTER_ULONG((PULONG)pHAC_TSR, (ULONG)(READ_REGISTER_ULONG(pHAC_TSR) & ~HAC_TSR_CMDAMT));

	i++;
	if (i>5) return FALSE;
	WRITE_REGISTER_ULONG((PULONG)pHAC_CSDR, RegData);	// Set data 
	WRITE_REGISTER_ULONG((PULONG)pHAC_CSAR, RegAddr);  // Set address

	BusyWait(AdjustMicroSecondsToLoopCount( 1 ));		// wait 1us
	WRITE_REGISTER_ULONG((PULONG)pHAC_CSAR, RegAddr);  // Set address

	if ( Wait_CSDR() == FALSE ) goto Retry;
	if ( Wait_CSAR() == FALSE ) goto Retry;

	//verify pHAC_CSAR
	if ( Wait_Status((ULONG)RegAddr) == FALSE ) goto Retry;

	return TRUE;
}

/*****************************************************************************
1234

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