📄 hssi.h
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//
// Copyright(C) Renesas Technology Corp. 1999-2005. All rights reserved.
//
// HSSIWaveDev Driver for ITS-DS7
//
//----------------------------------------------------------------------------
//
// FILE : HSSI.H
// CREATED : 1999.04.26 (for HD64465 on PFM-DS6)
// MODIFIED : 2005.02.25
// AUTHOR : Renesas Technology Corp.
// HARDWARE : RENESAS ITS-DS7
// FUNCTION : MDD-PDD interface layer of waveform audio driver
// HISTORY :
// 2003.06.20
// - Created release code.
// (based on WaveDev driver for ITS-DS6 Ver.2.2.0 for WCE4.1)
// 2005.02.25
// - Added SSI_SR_IIRQ_IDLE definition.
#include <windows.h>
#include <types.h>
#include <memory.h>
#include <excpt.h>
#include <waveddsi.h>
#include <wavedbg.h>
#include <mmsystem.h>
#include "shx.h"
#include "sh7770.h"
#include "platform.h"
#include "dma.h"
// Definitions for SSI
#define SSI_CH_REGBASE_OFFSET 0x00001000
#define SSI_REGSIZE (SSI0_REGSIZE+SSI1_REGSIZE+SSI2_REGSIZE+SSI3_REGSIZE)
// Register Offset
#define SSI_CR_OFFSET 0x0000
#define SSI_SR_OFFSET 0x0004
#define SSI_TDR_OFFSET 0x0008
#define SSI_RDR_OFFSET 0x000C
//
#define SSI_CR_DMEN_DISABLE 0x00000000
#define SSI_CR_DMEN_ENABLE 0x10000000
#define SSI_CR_UIEN_DISABLE 0x00000000
#define SSI_CR_UIEN_ENABLE 0x08000000
#define SSI_CR_OIEN_DISABLE 0x00000000
#define SSI_CR_OIEN_ENABLE 0x04000000
#define SSI_CR_IIEN_DISABLE 0x00000000
#define SSI_CR_IIEN_ENABLE 0x02000000
#define SSI_CR_DIEN_DISABLE 0x00000000
#define SSI_CR_DIEN_ENABLE 0x01000000
#define SSI_CR_MUEN_DISABLE 0x00000000
#define SSI_CR_MUEN_ENABLE 0x00000008
#define SSI_CR_CPEN_DISABLE 0x00000000
#define SSI_CR_CPEN_ENABLE 0x00000004
#define SSI_CR_TRMD_RECV 0x00000000
#define SSI_CR_TRMD_SEND 0x00000002
#define SSI_CR_EN_DISABLE 0x00000000
#define SSI_CR_EN_ENABLE 0x00000001
#define SSI_DISABLE_MASK 0x03FFFFFE // DMEN/UIEN/OIEN/EN off
#define SSI_ENABLE_MASK 0x1C000001 // DMEN/UIEN/OIEN/EN on
#define SSI_SR_IIRQ_IDLE 0x02000000
#define SSI_SR_DIRQ_TXEMPTY 0x01000000
#define SSI_SR_IDST_IDLE 0x00000001
// MODE
#define SSI_MASTER 1
#define SSI_SLAVE 0
// SSI1
#define SSI1_PLAY_MODE SSI_MASTER
#define SSI1_REC_MODE SSI_SLAVE
// SSI2
#define SSI2_PLAY_MODE SSI_MASTER
#define SSI2_REC_MODE SSI_SLAVE
// for I2C
#define CS4226_DSP_PMB_MASTER 0xe8 //
#define CS4226_DSP_PMB_SLAVE 0xc8 //
#define CS4226_APMB_MASTER 0xe8 //
#define CS4226_APMB_SLAVE 0x00 //
//#define CS4226_APMB_SLAVE 0xc8 //
#define CS4226_DACCB_NORMAL 0xc0 //
#define CS4226_DACCB_MUTE 0x3f //
// SSI CODEC_0
#define SSI1_CS4226_ReadADDR 0x20 // 00100000
#define SSI1_CS4226_WriteADDR 0x21 // 00100001
//#define SSI1_CS4226_PLAY_CMB 0x52 // for 11.025kHz
//#define SSI1_CS4226_REC_CMB 0x50 // for 11.025kHz
#define SSI1_CS4226_PLAY_CMB 0x00 // for 44.1kHz
#define SSI1_CS4226_REC_CMB 0x00 // for 44.1kHz
#define SSI1_CS4226_PLAY_DSP_PMB CS4226_DSP_PMB_SLAVE
#define SSI1_CS4226_REC_DSP_PMB CS4226_DSP_PMB_MASTER
#define SSI1_CS4226_PLAY_APMB CS4226_APMB_SLAVE
#define SSI1_CS4226_REC_APMB CS4226_APMB_MASTER
#define SSI1_CS4226_PLAY_DACCB CS4226_DACCB_NORMAL
#define SSI1_CS4226_REC_DACCB CS4226_DACCB_NORMAL
// SSI CODEC_1
#define SSI2_CS4226_ReadADDR 0x22 // 00100010
#define SSI2_CS4226_WriteADDR 0x23 // 00100011
//#define SSI2_CS4226_PLAY_CMB 0x40 // for 11.025kHz
//#define SSI2_CS4226_REC_CMB 0x40 // for 11.025kHz
#define SSI2_CS4226_PLAY_CMB 0x00 // for 44.1kHz
#define SSI2_CS4226_REC_CMB 0x00 // for 44.1kHz
#define SSI2_CS4226_PLAY_DSP_PMB CS4226_DSP_PMB_SLAVE
#define SSI2_CS4226_REC_DSP_PMB CS4226_DSP_PMB_SLAVE
#define SSI2_CS4226_PLAY_APMB CS4226_APMB_SLAVE
#define SSI2_CS4226_REC_APMB CS4226_APMB_SLAVE
#define SSI2_CS4226_PLAY_DACCB CS4226_DACCB_NORMAL
#define SSI2_CS4226_REC_DACCB CS4226_DACCB_MUTE
// CODEC register map
#define CODEC_NONE 0x00 // None
#define CODEC_CMB 0x01 // Clock Mode Byte(01h)
#define CODEC_CCB 0x02 // Converter Control Byte(02h)
#define CODEC_DAC_CB 0x03 // DAC Control Byte(03h)
#define CODEC_OADB 0x04 // Output Attenuator Data Byte(04h,05h,06h,07h,08h,09h)
#define CODEC_DAC_SRB 0x0A // DAC Status Report Byte(Read Only)(0Ah)
#define CODEC_ADC_CB 0x0B // ADC Control Byte(0Bh)
#define CODEC_ICB 0x0C // Input Control Byte(0Ch)
#define CODEC_ADC_SRB 0x0D // ADC Status Report Byte(Read Only)(0Dh)
#define CODEC_DSP_PMB 0x0E // DSP Port Mode Byte(0Eh)
#define CODEC_APMB 0x0F // Auxiliary Port Mode Byte(0Fh)
#define CODEC_APCB 0x10 // Auxilliary Port Control Byte(10h)
#define CODEC_RSB 0x11 // Receiver Status Byte(Read Only)(11h)
#define CODEC_RCSB 0x12 // Receiver Channel Status Byte(Read Only)(12h,13h,14h,15h,16h,17h,18h,19h)
#define CODEC_OADB_1 0x04 // Output Attenuator Data Byte(04h)
#define CODEC_OADB_2 0x05 // Output Attenuator Data Byte(05h)
#define CODEC_OADB_3 0x06 // Output Attenuator Data Byte(06h)
#define CODEC_OADB_4 0x07 // Output Attenuator Data Byte(07h)
#define CODEC_OADB_5 0x08 // Output Attenuator Data Byte(08h)
#define CODEC_OADB_6 0x09 // Output Attenuator Data Byte(09h)
#define CODEC_RCSB_A1 0x12 // Receiver Channel Status Byte(Read Only)(12h)
#define CODEC_RCSB_A2 0x13 // Receiver Channel Status Byte(Read Only)(13h)
#define CODEC_RCSB_A3 0x14 // Receiver Channel Status Byte(Read Only)(14h)
#define CODEC_RCSB_A4 0x15 // Receiver Channel Status Byte(Read Only)(15h)
#define CODEC_RCSB_B1 0x16 // Receiver Channel Status Byte(Read Only)(16h)
#define CODEC_RCSB_B2 0x17 // Receiver Channel Status Byte(Read Only)(17h)
#define CODEC_RCSB_B3 0x18 // Receiver Channel Status Byte(Read Only)(18h)
#define CODEC_RCSB_B4 0x19 // Receiver Channel Status Byte(Read Only)(19h)
// Converter Control Byte(02h)
#define CODEC_CCB_RS_NORESET 0x00
#define CODEC_CCB_RS_RESET 0x01
#define CODEC_CCB_RS_MASK CODEC_CCB_RS_RESET
// SSI Control Register for driver
typedef union _SSIControlRegister {
struct {
DWORD EN : 1; // HSSI Module Enable
DWORD TRMD : 1; // Transmit/Receive Mode Select
DWORD CPEN : 1; // Compressed Mode Enable
DWORD MUEN : 1; // Mute Enable
DWORD CKDV : 3; // Serial Oversample Clock Divide Ratio
DWORD BREN : 1; // Burst Mode Enable
DWORD DEL : 1; // Serial Data Delay
DWORD PDTA : 1; // Parallel Data Alignment
DWORD SDTA : 1; // Serial Data Alignment
DWORD SPDP : 1; // Serial Padding Polarity
DWORD SWSP : 1; // Serial WS Polarity
DWORD SCKP : 1; // Serial Clock Polarity
DWORD SWSD : 1; // Serial WS Direction
DWORD SCKD : 1; // Serial Clock Direction
DWORD SWL : 3; // System Word Length
DWORD DWL : 3; // Data Word Length
DWORD CHNL : 2; // Channels
DWORD DIEN : 1; // Data IRQ Enable
DWORD IIEN : 1; // Idle Mode IRQ Enable
DWORD OIEN : 1; // Overflow IRQ Enable
DWORD UIEN : 1; // Underflow IRQ Enable
DWORD DMEN : 1; // DMA Enable
DWORD Reserved : 3; // Reserved
} bits;
DWORD AsDWORD;
} SSIControlRegister;
extern PBYTE GetVirtualAddressOfUncachedMemory( PVOID, ULONG, char *);
extern BOOL dma_SetControl(PDMA_INFO, DWORD);
extern BOOL dma_SetCommand(PDMA_INFO, DWORD);
extern BOOL dma_InterruptEnable(PDMA_INFO);
extern BOOL dma_Stop(PDMA_INFO);
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