hspdif.h

WinCE5.0BSP for Renesas SH7770

//
// Copyright(C) Renesas Technology Corp. 2002-2003. All rights reserved.
//
// HSPDIF Driver for ITS-DS7
//
// FILE      : HSPDIF.H
// CREATED   : 2002.06.26
// MODIFIED  : 2003.12.03
// AUTHOR    : Renesas Technology Corp.
// HARDWARE  : RENESAS ITS-DS7
// HISTORY   : 
//             2003.06.20
//              - Created release code.
//                (based on HSPDIF driver for ITS-DS4 Ver.1.4.0 for WCEfA3.5)
//             2003.12.03
//              - common dma header included.
//

#include "dma.h"

// SPDIF Control Register for driver
typedef union _SPDIFControlRegister {
	struct {
		DWORD	TCBI : 1;	//  0 		Transmitter Channel Buffer Interrupt Enable
		DWORD	TCSI : 1;	//  1 		Transmitter Channel Status Interrupt Enable
		DWORD	RCBI : 1;	//  2 		Receiver Channel Buffer Interrupt Enable
		DWORD	RCSI : 1;	//  3 		Receiver Channel Status Interrupt Enable
		DWORD	ABUI : 1;	//  4? 		Audio Buffer Underrun Interrupt Enable
		DWORD	ABOI : 1;	//  5? 		Audio Buffer Overrun Interrupt Enable
		DWORD	TUII : 1;	//  6? 		Transmitter User Information Interupt Enable
		DWORD	RUII : 1;	//  7? 		Receiver User Information Interupt Enable
		DWORD	CSEI : 1;	//  8 		Channel Status Eror Interrupt Enable
		DWORD	PREI : 1;	//  9 		Preamble Error Interrupt Enable
		DWORD	PAEI : 1;	// 10 		Parity Error Interrupt Enable
		DWORD	CREI : 1;	// 11 		Clock Recovery Error Interrupt Enable
		DWORD	UBUI : 1;	// 12 		Use Buffer Underrun Interrupt Enable
		DWORD	UBOI : 1;	// 13 		Use Buffer Overrun Interrupt Enable
		DWORD	TEIE : 1;	// 14 		Transmitter Error Interrupt Enable
		DWORD	REIE : 1;	// 15 		Receiver Error Interrupt Enable
		DWORD	TME  : 1;	// 16 		Transmitter Module Enable
		DWORD	RME  : 1;	// 17 		Receiver Module Enable
		DWORD	AOS  : 1;	// 18 		Audio Only Samples
		DWORD	NCSI : 1;	// 19 		New Channel Status Information
		DWORD	TDE  : 1;	// 20 		Transmitter DMA Enable
		DWORD	RDE  : 1;	// 21 		Receiver DMA Enable
		DWORD	TASS : 2;	// 22-23 	Transmitter Audio Sample Bit Size
		DWORD	RASS : 2;	// 24-25 	Receiver Audio Sample Bit Size
		DWORD	PB   : 1;	// 26 		Pass Back
		DWORD	Res  : 5;	// 27-31	Reserved
	} bits;
	DWORD	AsDWORD;
} SPDIFControlRegister;

typedef struct _BITS_CONVERSION {
	DWORD	dwData;
	DWORD	dwShift;
	DWORD	dwDirection;
	DWORD	dwInc;
}BITS_CONVERSION, *PBITS_CONVERSION;

typedef struct _SPDIF_GLOBAL {

	DWORD		dwTxStatus; // use 4 byte
	DWORD		dwRxStatus; // use 4 byte

	BYTE		PAD[248];

} SPDIF_GLOBAL, *PSPDIF_GLOBAL;

typedef struct _SPDIF_DRIVER_INFO {
	PVBYTE		pvRegBase;					// Base address of registers

	DWORD		dwAccessOwner;				// Access code
	DWORD		dwStatus;					// The state of transmission and reception of operation

	// for SPDIF registers
	PVULONG		pvControl;					// Address of control register
	PVULONG		pvStatus;					// Address of status register

	// for ISR global

	PSPDIF_GLOBAL	pvGlobal;
	HANDLE		hInterrupt;
	HANDLE		hRxEvent;					// Interrupt event handler for RX
	HANDLE		hTxEvent;					// Interrupt event handler for TX


} SPDIF_DRIVER_INFO, *PSPDIF_DRIVER_INFO;

typedef struct _SPDIF_OPEN_INFO{
	PSPDIF_DRIVER_INFO	pInfo;				// PSPDIF_DRIVER_INFO
	DWORD		dwAccess;					// Access code
	DWORD		dwShareMode;				// Share mode

	BOOL		bTxThread;					// The status for TX Interrupt service thread
	PVBYTE		pvOutBufferBase;

	PVBYTE		pvOutWorkBuffer;
	DWORD		dwOutWorkWPtr;
	DWORD		dwOutWorkTPtr;

	HANDLE		hTxWaitEvent;
	DWORD		dwTxFlipBuff;
	DWORD		dwTxSampleSize;

	BITS_CONVERSION	*TxBits;
	DWORD		dwTxShiftPtr;
	DWORD		dwTxWork;
	CRITICAL_SECTION	TxCS;

	BOOL		bRxThread;					// The status for RX Interrupt Service Thread

	PVBYTE		pvInBufferBase;

	PVBYTE		pvInWorkBuffer;
	DWORD		dwInWorkWPtr;
	DWORD		dwInWorkRPtr;

	HANDLE		hRxWaitEvent;
	DWORD		dwRxFlipBuff;
	DWORD		dwRxSampleSize;

	BITS_CONVERSION	*RxBits;
	DWORD		dwRxRemainOffset;
	DWORD		dwRxShiftPtr;
	DWORD		dwRxWork;
	CRITICAL_SECTION	RxCS;

	PDMA_INFO	pTxDma;
	PDMA_INFO	pRxDma;

}SPDIF_OPEN_INFO, *PSPDIF_OPEN_INFO;


#define SPDIF_OUT_BUFFER_BASE		SPDIF_BUFFER_BASE
#define SPDIF_IN_BUFFER_BASE		(SPDIF_BUFFER_BASE+0x10000)
#define SPDIF_OUT_DMA_PAGE_SIZE		0x4000
#define SPDIF_IN_DMA_PAGE_SIZE		0x4000

#define SPDIF_WORK_OBUFFER_BASE		SPDIF_BUFFER_BASE2
#define SPDIF_WORK_OBUFFER_SIZE		0x00020000
#define SPDIF_WORK_IBUFFER_BASE		(SPDIF_WORK_OBUFFER_BASE+SPDIF_WORK_OBUFFER_SIZE)
#define SPDIF_WORK_IBUFFER_SIZE		0x00020000

#define SPDIF_TRANSMITTING			0x00000001
#define SPDIF_RECEIVING				0x00000002

BOOL StopTransmitting(PSPDIF_OPEN_INFO);
BOOL StopReceiving(PSPDIF_OPEN_INFO);
BOOL SPD_Close(PSPDIF_OPEN_INFO);
DWORD SPDIFInterruptThread(PSPDIF_DRIVER_INFO);
DWORD SPDIFInterruptThreadTx(PSPDIF_OPEN_INFO);
DWORD SPDIFInterruptThreadRx(PSPDIF_OPEN_INFO);
DWORD SPDIF_TransmittingData(PSPDIF_OPEN_INFO, PVOID, DWORD);
DWORD SPDIF_ReceivingData(PSPDIF_OPEN_INFO, PVOID, DWORD);
BOOL SPDIF_FillBuffer(PSPDIF_OPEN_INFO);
BOOL SPDIF_GetData(PSPDIF_OPEN_INFO);
VOID SPDIF_StopReceive(PSPDIF_OPEN_INFO);
VOID SPDIF_StopTransmit(PSPDIF_OPEN_INFO);
DWORD FillWorkBuffer(PSPDIF_OPEN_INFO, PVOID, DWORD);
DWORD GetWorkBuffer(PSPDIF_OPEN_INFO, PVOID, DWORD);

VOID ConvertTo32Bits(PSPDIF_OPEN_INFO);
VOID ConvertFrom32Bits(PSPDIF_OPEN_INFO);

// Operate the row of bits.
#define SHIFT_N	0
#define SHIFT_R	1
#define SHIFT_L	2
#define INC_DST	1
#define INC_SRC	2


#define SPDIF_REG_OFFSET		0x00000000
#define SPDIF_TLCA_OFFSET		(SPDIF_REG_OFFSET+0x00000000)
#define SPDIF_TRCA_OFFSET		(SPDIF_REG_OFFSET+0x00000004)
#define SPDIF_TLCS_OFFSET		(SPDIF_REG_OFFSET+0x00000008)
#define SPDIF_TRCS_OFFSET		(SPDIF_REG_OFFSET+0x0000000c)
#define SPDIF_TUI_OFFSET		(SPDIF_REG_OFFSET+0x00000010)
#define SPDIF_RLCA_OFFSET		(SPDIF_REG_OFFSET+0x00000014)
#define SPDIF_RRCA_OFFSET		(SPDIF_REG_OFFSET+0x00000018)
#define SPDIF_RLCS_OFFSET		(SPDIF_REG_OFFSET+0x0000001c)
#define SPDIF_RRCS_OFFSET		(SPDIF_REG_OFFSET+0x00000020)
#define SPDIF_RUI_OFFSET		(SPDIF_REG_OFFSET+0x00000024)
#define SPDIF_CTRL_OFFSET		(SPDIF_REG_OFFSET+0x00000028)
#define SPDIF_STAT_OFFSET		(SPDIF_REG_OFFSET+0x0000002c)
#define SPDIF_TDAD_OFFSET		(SPDIF_REG_OFFSET+0x00000030)
#define SPDIF_RDAD_OFFSET		(SPDIF_REG_OFFSET+0x00000034)