📄 startup.src
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;
; Copyright(C) Renesas Technology Corp. 1998-2003. All rights reserved.
;
; NK Kernel for ITS-DS7 Ver.1.0.0
;
; FILE : startup.src
; CREATED : 2002.04.25
; MODIFIED : 2003.06.20
; AUTHOR : Renesas Technology Corp.
; HARDWARE : RENESAS ITS-DS7
; HISTORY :
; 2003.06.20
; - Created release code.
; (based on RENESAS ITS-DS4 Source Kit Ver.1.2.0 for WCE4.2)
; 2005.08.10
; - Changed OAL file and directory structures to production-qualiry OAL model.
; changed filename from fw.src to startup.src.
;++
; THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
; ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
; PARTICULAR PURPOSE.
; Copyright (c) 1995-2000 Microsoft Corporation. All rights reserved.
;
; Module Name:
; This module implements the code necessary to initialize the P2 HW and
; Kernel interface routines.
;
; Abstract:
;
; Functions:
;
;
; Notes:
;
;--
.include "kxshx.h"
.include "shx.inc"
.include "platform.inc"
.include "sh7770.inc"
.include "boot.inc"
.include "oalintr.inc"
.include "drv_glob.inc"
.section .text,code
.align 4
.export _SH4CacheLines
_SH4CacheLines: .data.l 1024 ;256entry/way (SH4A is 4way)
.import KernelStart
.import _OEMInitDebugSerial
;******************************************************************************
;* FUNCTION : StartUp()
;* DESCRIPTION : The initial starting point of the system
;* INPUTS : None - we are branched to from the reset vector
;* OUTPUTS : None, we branch to the main()
;******************************************************************************
LEAF_ENTRY _StartUp
mova strt10, r0
mov #h'20000000, r2 ; moves from section P1(cached) to P2 (uncached)
or r2, r0
jmp @r0 ; jumps to strt10 in section P2
nop
.align 4
strt10:
mov.l #h'53, r2 ; 'S'
mov.l #LED_ALPHA, r3
mov.b r2, @r3
mov.l #h'74, r2 ; 't'
add #LED_ALPHA_STRIDE, r3
mov.b r2, @r3
mov.l #h'61, r2 ; 'a'
add #LED_ALPHA_STRIDE, r3
mov.b r2, @r3
mov.l #h'72, r2 ; 'r'
add #LED_ALPHA_STRIDE, r3
mov.b r2, @r3
mov.l #h'74, r2 ; 't'
add #LED_ALPHA_STRIDE, r3
mov.b r2, @r3
mov.l #h'55, r2 ; 'U'
add #LED_ALPHA_STRIDE, r3
mov.b r2, @r3
mov.l #h'70, r2 ; 'p'
add #LED_ALPHA_STRIDE, r3
mov.b r2, @r3
mov.l #h'25, r2 ; '%'
add #LED_ALPHA_STRIDE, r3
mov.b r2, @r3
mov.l #TM_SR, r0 ; release mask etc
ldc r0, sr
; the very fist thing is to initialize the Watch Dog timer.
mov #RESET_WDTCSR, r1
mov #RESET_WDTCSR_COOKIE, r0
mov.w r0, @r1 ; Set TME bit of WDTCSR to 0
mov #RESET_WDTBCNT, r1
mov #RESET_WDTBCNT_MAXVALUE, r0
mov.w r0, @r1 ; Set type of clock count to use in WTCSR
mov #RESET_WDTCNT, r1
mov #RESET_WDTCNT_COOKIE, r0
mov.w r0, @r1 ; Set initial value for counter in WDTCNT
;---------------------------------------------------------------------------
;
; MemoryController, CPG, Busbridge, Busbridge BSC are initialized in EBOOT.
;
;---------------------------------------------------------------------------
; Disable the Cache, the kernel will take care of it.
mov #CCN_CCR, r1 ; ptr to Cache control register
mov #CCN_CCR_DISABLE, r0
mov.l r0, @r1 ; disable the cache
; Load the Kernel and JUMP
mov #KernelStart, r0 ; load address of KernelStart
mov #h'20000000, r2 ; moves from section P1(cached) to P2 (uncached)
or r2, r0
jmp @r0 ; execute KernelStart in P1 section
nop
.endf
;*****************************************************************************
;* OEMPowerOff - OFF button handler
;*
;* This routine is invoked when the OFF button is pressed. It is responsible
;* for any final power off state and putting the cpu into standby.
;*
;* Entry none
;* Exit none
;* Uses r0-r3
;*****************************************************************************
; LEAF_ENTRY _OEMPowerOff
; Don't power down if image is loaded into RAM
;// del mov #h'0C000000, r0
;// del sts PR, r1
;// del and r1,r0
;// del tst r0,r0
;// del bf OemPwrOffExit
;Save registers on stack
;// del stc.l SR, @-r15
;// del sts.l PR, @-r15
;// del stc.l VBR, @-r15
;Unmask interrupts above pri 3 for resume,set block bit,use reg bank1
;// del mov.l #h'70000010, r0
;// del ldc r0, SR
;Save TSTR on stack
; mov.l #TMU_TSTR0,r0 ; (r0) = ptr timer start register
;// del mov.l #TSTR0_GLOBAL,r0 ; (r0) = ptr timer start register
;// del mov.b @r0,r1 ; (r1) = timer start register
;// del mov.l r1,@-r15 ; store timer start register
;Set STBCR
; mov.l #CPG_STBCR, r0 ; (r0) = ptr standby control register
; mov.b @r0,r1 ; (r1) = standby control register
; mov.l r1,@-r15 ; store standby control register
; mov #CPG_STBCR_STBY,r2 ; (r2) = STBY bit(n/7) on
; or r2,r1 ; standby control register STBY bit on
; mov.b r1, @r0 ; set standby control register
;Set CPG (CPUclock=100MHz)
; mov.l #CPG_FRQCR, r0 ; (r0) = ptr frequency control register
; mov.w @r0,r1 ; (r1) = frequency control registe
; mov.l r1,@-r15 ; store frequency control register
; mov.w #CPG_FRQCR_CLOCK2, r1 ; (r1) = (CPUclock = 100MHz)
; mov.w r1, @r0 ; set frequency control register
;Enter Self Refresh mode
; mov.l #BSC_MCR,r0 ; (r0) = ptr memory control register
; mov.l @R0,r1 ; (r1) = memory control register
; mov.l #(BSC_MCR_RFSH + BSC_MCR_RMODE), r2 ; (r2) = RFSH(n/1) and RMODE(n/0) bit on
; or r2, r1 ; memory control register RFSH and RMODE bit set
; mov.l r1, @r0 ; set memory control register
;Set WDT control
; mov.l #CPG_WTCSR,r0 ; (r0) = ptr control / state register
; mov.w @r0,r1 ; (r1) = control / state register
; mov.w #(CPG_WTCSR_COOKIE + CPG_WTCSR_CKS_4096),r1
; (r1) = WTCSR_COOKIE(h'a500) + CK2(n/2) ,CK1(n/1), CK0(n/0) bit on
; mov.w r1,@r0 ; set control / state register
;Set WDT count
; mov.l #CPG_WTCNT,r0 ; (r0) = ptr timer count register
; mov.w @r0,r1 ; (r1) = timer count register
; mov.w #(CPG_WTCNT_COOKIE + h'00ff),r1 ; (r1) = WTCNT_COOKIE(h'5a00) + full count(h'00ff)
; mov.w r1,@r0 ; set timer count register
;Set up int handler for wakeup
;// del mov.l #Resume, r0 ; (r0) = ptr Resume
;// del mov.l #h'600, r1
;// del sub r1, r0
;// del ldc r0, vbr
;Enter Standby mode
;// del sleep
;// del .align 4
;// del Resume: ; resume cpu
;Restore MCR
; mov #BSC_MCR,r2 ; Set memory control,
;
; .aif SDRAM_MODULE eq h'01
; mov #BSC_MCR_MEM_TYPE_SDRAM, r0 ; based on val in init.src
; .aelse
; mov #BSC_MCR_MEM_TYPE_EDO, r0 ; based on val in init.src
; .aendi
;
; mov.l r0, @r2
; .aif SDRAM_MODULE eq h'01
; mov.l #h'FF940190, r1
; mov.b r1, @r1
;
;MCR_timer2:
; mov.l #h'0000fff0, r0
;
;MCR_loop2:
; add #(-1), r0
; tst r0, r0
; bf MCR_loop2
;
; mov #BSC_MCR, r2
; mov #BSC_MCR_SDRAM_MRSET, r0
; mov.l r0, @r2 ;265 12 bit cas
; mov.l #h'FF940190, r1
; mov.b r1, @r1
; .aendi
;Restore CPG(CPUclock=200MHz)
; mov.l #CPG_FRQCR, r0 ; (r0) = ptr frequency control register
; mov.l @r15+,r1 ; restor frequency control register
; mov.w r1, @r0 ; set frequency control register
;Wait 10ms for HD64465 clock steady
; mov.l #h'00200000,r1
;Wait_Loop:
; dt r1
; bf Wait_Loop
; nop
;Restore STBCR
; mov.l #CPG_STBCR, r0 ; (r0) = ptr standby control register
; mov.l @r15+,r1 ; restor standby control register
; mov.b r1,@r0 ; set standby control register
;Restore TSTR
; mov.l #TMU_TSTR0,r0 ; (r0) = ptr timer start register
;// del mov.l #TSTR0_GLOBAL,r0 ; (r0) = ptr timer start register
;// del mov.l @r15+,r1 ; restor timer start register
;// del mov.b r1,@r0 ; set timer start register
;Initialize debug serial/ethernet port
;// del mov r4, @-r15
;// del mov r5, @-r15
;// del mov r6, @-r15
;// del mov r7, @-r15
;// del mov.l #_OEMInitDebugSerial, r0 ; (r0) = ptr debugSerial/ethernet port
;// del jsr @r0 ; initialize debugSerial/ethernet port
;// del nop
;Restore registers
;// del mov @r15+, r7
;// del mov @r15+, r6
;// del mov @r15+, r5
;// del mov @r15+, r4
;Restore registers
;// del ldc.l @r15+, VBR
;// del lds.l @r15+, PR
;// del ldc.l @r15+, SR
;// del OemPwrOffExit:
; rts
; nop
; .endf
;*****************************************************************************
; CPUEnterIdle
; NOTE: Exceptions are blocked when this routine called and must not
; be reenabled unless the functions is going to return immediately.
; The SH3 ignores the block bit in the PSR when sleeping so it is
; not necessary to enable interrupts before issuing the sleep
; instruction.
;*****************************************************************************
LEAF_ENTRY _CPUEnterIdle
sleep
rts
nop
.endf
;*****************************************************************************
;* OEMIdle - system idle
;*
;* This routine is called by the kernel when there are no threads ready to
;* run. The CPU should be put into a reduced power mode and halted. It is important
;* to be able to resume execution quickly upon receiving an interrupt.
;*
;* NOTE: Exceptions are blocked when this routine called and must not be reenabled
;* unless the functions is going to return immediately. The SH4 ignores the block bit
;* in the PSR when sleeping so it is not necessary to enable interrupts before issuing
;* the sleep instruction.
;*
;* Entry Exceptions blocked
;* Exit none
;* Uses r0-r3
;*****************************************************************************
; LEAF_ENTRY OEMIdle
; sleep
; rts
; nop
; .endf
;*****************************************************************************
;* OEMNMI - non-maskable interrupt handler
;*
;* This routine is called when a non-maskable interrupt occurs. It should return
;* an interrupt cause the same as other interrupt service routines.
;*
;* Registers: r0-r3,r6 available for use.
;*
;* Entry in register bank 1, exceptions blocked
;* Exit (r0) = interrupt dispostion information
;* (see nkintr.h for values)
;* Uses r0
;*****************************************************************************
LEAF_ENTRY OEMNMI
rts
mov #SYSINTR_NOP, r0
.endf
.end
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