kdioctl.c

WinCE5.0BSP for Renesas SH7770

//
//  Copyright(C) Renesas Technology Corp. 2005. All rights reserved.
//
//  generic IOCTLs for ITS-DS7 Ver.0.8.0
//
//  FILE      : kdioctl.c
//  CREATED   : 2005.08.10
//  MODIFIED  : 
//  AUTHOR    : Renesas Technology Corp.
//  HARDWARE  : RENESAS ITS-DS7
//  HISTORY   : 
//              2005.08.10
//              - Created release code.
//                (based on SMDK2410/MAINSTONEII for WCE5.0)
//

//
// KD Ioctl routines
//
#include "windows.h"
#include "platform.h"
#include <pkfuncs.h>

#if defined(SHx) 

#define RWE_DISABLE     0x0    // Disables BP
#define RWE_READ        0x1
#define RWE_WRITE       0x2
#define RWE_READWRITE   0x3

#define CON_DISABLE     0x0    // Disables BP
#define CON_INST        0x1
#define CON_DATA        0x2
#define CON_BOTH        0x3

#define FULL_ADDR_ENABLE 0x0
#define ASID_DISABLE     0x4
typedef struct _BREAK_BUS_CYCLE *PBREAK_BUS_CYCLE;
typedef struct _BREAK_BUS_CYCLE {
    USHORT      Size    : 2;
    USHORT      R_WSel  : 2;
    USHORT      I_DSel  : 2;
    USHORT      Pad     : 10;
} BREAK_BUS_CYCLE;

#if defined(SHx)

//
// User Break Controller memory-mapped addresses
//
#if SH4
#define UBCBarA  0xFF200000        // 32 bit Break Address A
#define UBCBamrA 0xFF200004        // 8 bit  Break Address Mask A
#define UBCBbrA  0xFF200008        // 16 bit Break Bus Cycle A
#define UBCBasrA 0xFF000014        // 8 bit  Break ASID A
#define UBCBarB  0xFF20000C       // 32 bit Break Address B
#define UBCBamrB 0xFF200010       // 8 bit  Break Address Mask B
#define UBCBbrB  0xFF200014       // 16 bit Break Bus Cycle A
#define UBCBasrB 0xFF000018       // 8 bit  Break ASID B
#define UBCBdrB  0xFF200018       // 32 bit Break Data B
#define UBCBdmrB 0xFF20001C       // 32 bit Break Data Mask B
#define UBCBrcr  0xFF200020       // 16 bit Break Control Register
#else
#define UBCBarA    0xffffffb0
#define UBCBamrA   0xffffffb4
#define UBCBbrA    0xffffffb8
#define UBCBasrA   0xffffffe4
#define UBCBarB    0xffffffa0
#define UBCBamrB   0xffffffa4
#define UBCBbrB    0xffffffa8
#define UBCBasrB   0xffffffe8
#define UBCBdrB    0xffffff90
#define UBCBdmrB   0xffffff94
#define UBCBrcr    0xffffff98
#endif
#endif

#define CLEARUBCA \
			    WRITE_REGISTER_ULONG(UBCBarA,  0); \
				WRITE_REGISTER_USHORT(UBCBrcr, 0); \
			    WRITE_REGISTER_UCHAR(UBCBamrA, 0); \
			    WRITE_REGISTER_USHORT(UBCBbrA, 0); \
			    WRITE_REGISTER_UCHAR(UBCBasrA, 0); 

#define CLEARUBCB \
			    WRITE_REGISTER_ULONG(UBCBarB,  0); \
				WRITE_REGISTER_USHORT(UBCBrcr, 0); \
			    WRITE_REGISTER_UCHAR(UBCBamrB, 0); \
			    WRITE_REGISTER_USHORT(UBCBbrB, 0); \
			    WRITE_REGISTER_UCHAR(UBCBasrB, 0); 
			    
USHORT BreakBusCycle = 0;

BOOL OEMKDIoControl( DWORD dwIoControlCode, LPVOID lpBuf, DWORD nBufSize)
{
	switch(dwIoControlCode) {
	case KD_IOCTL_INIT:
		CLEARUBCA;
		CLEARUBCB;
		return TRUE;
	case KD_IOCTL_SET_CBP:
	case KD_IOCTL_CLEAR_CBP:
	case KD_IOCTL_ENUM_CBP:
		break;
	case KD_IOCTL_QUERY_CBP:
		((PKD_BPINFO)lpBuf)->ulCount = 0;
		return TRUE;
	case KD_IOCTL_SET_DBP:
		{
			PBREAK_BUS_CYCLE pbbc = (PBREAK_BUS_CYCLE)&BreakBusCycle;
			if (!READ_REGISTER_ULONG(UBCBarA)) {
				BreakBusCycle = 0;
				pbbc->R_WSel = RWE_WRITE;
				pbbc->I_DSel = CON_DATA;
			    WRITE_REGISTER_ULONG(UBCBarA,  ((PKD_BPINFO)lpBuf)->ulAddress);
				WRITE_REGISTER_USHORT(UBCBrcr, 0);
			    WRITE_REGISTER_UCHAR(UBCBamrA, FULL_ADDR_ENABLE | ASID_DISABLE);
			    WRITE_REGISTER_USHORT(UBCBbrA, BreakBusCycle); 
			    WRITE_REGISTER_UCHAR(UBCBasrA, 0);
				((PKD_BPINFO)lpBuf)->ulHandle = 1;
				return TRUE;
			} 
			if (!READ_REGISTER_ULONG(UBCBarB)) {
				BreakBusCycle = 0;
				pbbc->R_WSel = RWE_WRITE;
				pbbc->I_DSel = CON_DATA;
			    WRITE_REGISTER_ULONG(UBCBarB,  ((PKD_BPINFO)lpBuf)->ulAddress);
				WRITE_REGISTER_USHORT(UBCBrcr, 0);
			    WRITE_REGISTER_UCHAR(UBCBamrB, FULL_ADDR_ENABLE | ASID_DISABLE);
			    WRITE_REGISTER_USHORT(UBCBbrB, BreakBusCycle); 
			    WRITE_REGISTER_UCHAR(UBCBasrB, 0);
				((PKD_BPINFO)lpBuf)->ulHandle = 2;
				return TRUE;
			}
		}
		break;
	case KD_IOCTL_CLEAR_DBP:
		if (((PKD_BPINFO)lpBuf)->ulHandle == 1) {
			CLEARUBCA
			return TRUE;
		} 
		if (((PKD_BPINFO)lpBuf)->ulHandle == 2) {
			CLEARUBCB
			return TRUE;
		} 
		break;
	case KD_IOCTL_QUERY_DBP:
		((PKD_BPINFO)lpBuf)->ulCount = 2;
		return TRUE;
	case KD_IOCTL_ENUM_DBP:
		break;
	case KD_IOCTL_MAP_EXCEPTION:
		if (((PKD_EXCEPTION_INFO)lpBuf)->ulExceptionCode == 0x80000113) {
			((PKD_EXCEPTION_INFO)lpBuf)->ulExceptionCode = STATUS_BREAKPOINT;
			return TRUE;
		}
		break;		
    case KD_IOCTL_DMPGEN_START:
        // Start of error report dump file generation into reserved memory
    case KD_IOCTL_DMPGEN_END:
        // End of error report dump file generation into reserved memory
        break;
	case KD_IOCTL_RESET:
        //*((volatile DWORD *) (CPU_BASE + CPU_RR)) |= 1;
        return TRUE;
	default:
		break;
	}
	return FALSE;
}

#endif