shdelay.src

WinCE5.0BSP for Renesas SH7770

;
;   Copyright(C) Renesas Technology Corp. 1998-2003. All rights reserved.
;
;   DrvLib for ITS-DS7
;
;   FILE      : drvsleep.c
;   CREATED   : 1999.04.26
;   MODIFIED  : 2003.06.20
;   AUTHOR    : Renesas Technology Corp.
;   HARDWARE  : RENESAS ITS-DS7
;   HISTORY   : 
;               2003.06.20
;               - Created release code.
;

	.include "kxshx.h"
	.include "shx.inc"
	.include "platform.inc"

;==============================================================================
; clock cycle time calculations
; assume: SH4 instruction times (2 cycles/loop iteration) CYCLES
;         33.333 MHz (SPEED)
;         no delay in the cache (0 cycle delay from cache->instruction pipeline)
;         and 6x overdrive (OVERDRIVE)
;         ignore overhead loading into cache and jsr/rts
;         input in microseconds
;
; loop count = delay time * conversion factor
; conversion factor = (SPEED*OVERDRIVE)/(CYCLES*10^6)
;
; result is divided into a 32.32 bit fixed point number
; 199.98 MHz -> 99

CLOCK_HIGH: .equ    0x00000063	; 99
CLOCK_LOW:  .equ    0x00000000	; 0

;/*****************************************************************************
;*	FUNCTION :		_AdjustMicroSecondsToLoopCount
;*	DESCRIPTION :	convert micro seconds to loop count
;*	INPUTS :		DWORD dwLoopCount - the number of iterations to loop
;*	OUTPUTS :		void
;*	DESIGN NOTES :	
;*	CAUTIONS :		this function only works for BusyWait and
;*					the InlineDelay macro in shdelay.h
;*					THE CALCULATION MUST BE REDONE FOR DIFFERENT
;*					CLOCK SPEEDS, CACHE SPEEDS, or DIFFERENT CPUs
;*					This function uses the stack, so it doesn't work in ISRs
;*  LIMITS :		The time limit to wait is about 100-200 seconds
;*					(4 billion / 1 million / 20(or27))
;*****************************************************************************/

	LEAF_ENTRY _AdjustMicroSecondsToLoopCount

	; clock parameters
	mov     #CLOCK_HIGH,r0
	mov     #CLOCK_LOW,r1

	; using 32x32->64 bit and 32x32->32 bit multiplies:
	; r0 = ((CLKH << 32) * delay + CLKL * delay ) >> 32
	dmulu.l r4,r1
	sts     mach,r1
	mul.l	r4,r0
	sts     macl,r0
	rts
	add	    r1,r0						; delayed slot, result into r0

	ENTRY_END _AdjustMicroSecondsToLoopCount

;/*****************************************************************************
;*	FUNCTION :		_BusyWait
;*	DESCRIPTION :	tight assembly loop for a busy wait
;*	INPUTS :		R4 = DWORD dwLoopCount - the number of iterations to loop
;*	OUTPUTS :		void
;*	DESIGN NOTES :	
;*	CAUTIONS :		This has a roughly proportional relation to REAL time!
;*					a small extra delay needs to be added in for subroutine
;*					linkage and cache load delays which is not considered
;*					in the calculation from clock speed to real time
;*					(use the InlineBusyWait macro for smaller overhead delays)
;*****************************************************************************/

; Note that SH-4 can execute 2 instraction in same cycle, and the 'bf/s' and
; the following 'dt' are executed together. Branch causes 1 stall cycle so
; total 2 clock cycles are required for 1 loop execution.

	LEAF_ENTRY _BusyWait

	tst     r4,r4		; delay already zero? (1 clock)
delay:
	bf/s    delay		; delayed slot branch   (2 clocks, 1 when done)
	dt      r4			; decrement count & test for 0 (1 clock)
	rts					; done
	nop

	ENTRY_END _BusyWait

	.end