oem.c

WinCE5.0BSP for Renesas SH7770

    case SYSINTR_GPIO:
        break;

    case SYSINTR_HAC:
        break;

    case SYSINTR_HSPDIF:
        WRITE_REGISTER_ULONG(INTC2MSKRG, INTC2MSKRG_HSPDIF);		// INTC2 HSPDIF Interrupts mask
        break;

    case SYSINTR_I2C:
        break;

    case SYSINTR_HSSI1:
        break;

    case SYSINTR_HSSI2:
        break;

    case SYSINTR_SRC:
        break;

    case SYSINTR_DU:
        WRITE_REGISTER_ULONG(INTC2MSKRG, INTC2MSKRG_DU);			// INTC2 DU Interrupts mask
        break;

    case SYSINTR_VIN:
        WRITE_REGISTER_ULONG(INTC2MSKRG, INTC2MSKRG_VIN);			// INTC2 VIN Interrupts mask
        break;

    case SYSINTR_IR:
        break;

    case SYSINTR_USB:
        break;

    case SYSINTR_ATAPI:
        break;

    case SYSINTR_2DG:
        WRITE_REGISTER_ULONG(INTC2MSKRG, INTC2MSKRG_2D);			// INTC2 2D Interrupts mask
        break;

    case SYSINTR_3DG:
    case SYSINTR_3DG_DMAC:
        WRITE_REGISTER_ULONG(INTC2MSKRG, INTC2MSKRG_3D);			// INTC2 3D Interrupts mask
        break;

    case SYSINTR_SCIF0:
        break;

    case SYSINTR_ADC:
        WRITE_REGISTER_ULONG(INTC2MSKRG, INTC2MSKRG_ADC | INTC2MSKRG_ADCIF);	// INTC2 ADC Interrupts mask
        break;

    }
    INTERRUPTS_ON();
}

//------------------------------------------------------------------------------
//
//  Function: OEMInterruptDone
//
//  OEMInterruptDone is called by the kernel when a device driver
//  calls InterruptDone(). The system is not preemtible when this
//  function is called.
//
VOID OEMInterruptDone(DWORD sysIntr)
{
    int		index, ch;

    INTERRUPTS_OFF();

    switch (sysIntr) {

    case SYSINTR_BREAK:
        break;

    case SYSINTR_RTC_ALARM:
        break;

    case SYSINTR_TIMING:
        break;

    case SYSINTR_ETHER:
        WRITE_REGISTER_ULONG(INTC_INTMSKCLR0, INTC_INTMSKCLR0_IC00);	// IRQ0 Interrupt Mask Clear
		WRITE_REGISTER_USHORT(SF_IRQ0MR, READ_REGISTER_USHORT(SF_IRQ0MR) & ~SF_IRQ0MR_LAN);		// IRQ0 Interrupts mask clear(LAN)
        break;

    case SYSINTR_PCMCIA_STATE:
        WRITE_REGISTER_ULONG(INTC_INTMSKCLR0, INTC_INTMSKCLR0_IC00);	// IRQ0 Interrupt Mask Clear
		WRITE_REGISTER_USHORT(SF_IRQ0MR, READ_REGISTER_USHORT(SF_IRQ0MR) & ~(SF_IRQ0MR_PCC0|SF_IRQ0MR_PCC1));		// IRQ0 Interrupts mask (PCC0/PCC1)
        break;

    case SYSINTR_PCMCIA_LEVEL:
        WRITE_REGISTER_ULONG(INTC_INTMSKCLR0, INTC_INTMSKCLR0_IC00);	// IRQ0 Interrupt Mask Clear
		WRITE_REGISTER_USHORT(SF_IRQ0MR, READ_REGISTER_USHORT(SF_IRQ0MR) & ~(SF_IRQ0MR_PCC0));		// IRQ0 Interrupts mask (PCC0)
        break;

    case SYSINTR_PCMCIA_LEVEL_1:
        WRITE_REGISTER_ULONG(INTC_INTMSKCLR0, INTC_INTMSKCLR0_IC00);	// IRQ0 Interrupt Mask Clear
		WRITE_REGISTER_USHORT(SF_IRQ0MR, READ_REGISTER_USHORT(SF_IRQ0MR) & ~(SF_IRQ0MR_PCC1));		// IRQ0 Interrupts mask (PCC1)
        break;

    case SYSINTR_GPIO:
        WRITE_REGISTER_ULONG(INTC2MSKCR, INTC2MSKCR_GPIO);		// GPIO Interrupt Mask Clear
        break;

    case SYSINTR_HAC:
	index = READ_REGISTER_ULONG(DRV_GLOBAL_BASE + AUD_INDEX_HAC_OFFSET);
	ch    = READ_REGISTER_ULONG(DRV_GLOBAL_BASE + (sizeof(AUDIO_GLOBALS) * index) + PLAY_CH_OFFSET);
	if( READ_REGISTER_UCHAR(DRV_GLOBAL_BASE + DMA_INTERRUPT_FLG_OFFSET + ch) ){
		WRITE_REGISTER_UCHAR(DRV_GLOBAL_BASE + DMA_INTERRUPT_FLG_OFFSET + ch, (UCHAR)0);
		WRITE_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET,
			READ_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET) | ((ULONG)1 << ch));
	}
	ch    = READ_REGISTER_ULONG(DRV_GLOBAL_BASE + (sizeof(AUDIO_GLOBALS) * index) + REC_CH_OFFSET);
	if( READ_REGISTER_UCHAR(DRV_GLOBAL_BASE + DMA_INTERRUPT_FLG_OFFSET + ch) ){
		WRITE_REGISTER_UCHAR(DRV_GLOBAL_BASE + DMA_INTERRUPT_FLG_OFFSET + ch, (UCHAR)0);
		WRITE_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET,
			READ_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET) | ((ULONG)1 << ch));
	}
        break;

    case SYSINTR_HSPDIF:
		WRITE_REGISTER_UCHAR(DRV_GLOBAL_BASE + DMA_INTERRUPT_FLG_OFFSET + CH_TX_HSPDIF, (UCHAR)0);
		WRITE_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET,
			READ_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET) | ((ULONG)1 << CH_TX_HSPDIF));
		WRITE_REGISTER_UCHAR(DRV_GLOBAL_BASE + DMA_INTERRUPT_FLG_OFFSET + CH_RX_HSPDIF, (UCHAR)0);
		WRITE_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET,
			READ_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET) | ((ULONG)1 << CH_RX_HSPDIF));
        break;

    case SYSINTR_I2C:
    	WRITE_REGISTER_ULONG(INTC2MSKCR, INTC2MSKCR_I2C);		// I2C Interrupt Mask Clear
        break;

    case SYSINTR_HSSI1:
	index = READ_REGISTER_ULONG(DRV_GLOBAL_BASE + AUD_INDEX_HSSI1_OFFSET);
	ch    = READ_REGISTER_ULONG(DRV_GLOBAL_BASE + (sizeof(AUDIO_GLOBALS) * index) + PLAY_CH_OFFSET);
	if( READ_REGISTER_UCHAR(DRV_GLOBAL_BASE + DMA_INTERRUPT_FLG_OFFSET + ch) ){
		WRITE_REGISTER_UCHAR(DRV_GLOBAL_BASE + DMA_INTERRUPT_FLG_OFFSET + ch, (UCHAR)0);
		WRITE_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET,
			READ_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET) | ((ULONG)1 << ch));
	}
	ch    = READ_REGISTER_ULONG(DRV_GLOBAL_BASE + (sizeof(AUDIO_GLOBALS) * index) + REC_CH_OFFSET);
	if( READ_REGISTER_UCHAR(DRV_GLOBAL_BASE + DMA_INTERRUPT_FLG_OFFSET + ch) ){
		WRITE_REGISTER_UCHAR(DRV_GLOBAL_BASE + DMA_INTERRUPT_FLG_OFFSET + ch, (UCHAR)0);
		WRITE_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET,
			READ_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET) | ((ULONG)1 << ch));
	}
		break;

    case SYSINTR_HSSI2:
	index = READ_REGISTER_ULONG(DRV_GLOBAL_BASE + AUD_INDEX_HSSI2_OFFSET);
	ch    = READ_REGISTER_ULONG(DRV_GLOBAL_BASE + (sizeof(AUDIO_GLOBALS) * index) + PLAY_CH_OFFSET);
	if( READ_REGISTER_UCHAR(DRV_GLOBAL_BASE + DMA_INTERRUPT_FLG_OFFSET + ch) ){
		WRITE_REGISTER_UCHAR(DRV_GLOBAL_BASE + DMA_INTERRUPT_FLG_OFFSET + ch, (UCHAR)0);
		WRITE_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET,
			READ_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET) | ((ULONG)1 << ch));
	}
	ch    = READ_REGISTER_ULONG(DRV_GLOBAL_BASE + (sizeof(AUDIO_GLOBALS) * index) + REC_CH_OFFSET);
	if( READ_REGISTER_UCHAR(DRV_GLOBAL_BASE + DMA_INTERRUPT_FLG_OFFSET + ch) ){
		WRITE_REGISTER_UCHAR(DRV_GLOBAL_BASE + DMA_INTERRUPT_FLG_OFFSET + ch, (UCHAR)0);
		WRITE_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET,
			READ_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET) | ((ULONG)1 << ch));
	}
        break;

    case SYSINTR_SRC:
	index = READ_REGISTER_ULONG(DRV_GLOBAL_BASE + AUD_INDEX_SRC_OFFSET);
	ch    = READ_REGISTER_ULONG(DRV_GLOBAL_BASE + (sizeof(AUDIO_GLOBALS) * index) + PLAY_CH_OFFSET);
	if( READ_REGISTER_UCHAR(DRV_GLOBAL_BASE + DMA_INTERRUPT_FLG_OFFSET + ch) ){
		WRITE_REGISTER_UCHAR(DRV_GLOBAL_BASE + DMA_INTERRUPT_FLG_OFFSET + ch, (UCHAR)0);
		WRITE_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET,
			READ_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET) | ((ULONG)1 << ch));
	}
	ch    = READ_REGISTER_ULONG(DRV_GLOBAL_BASE + (sizeof(AUDIO_GLOBALS) * index) + REC_CH_OFFSET);
	if( READ_REGISTER_UCHAR(DRV_GLOBAL_BASE + DMA_INTERRUPT_FLG_OFFSET + ch) ){
		WRITE_REGISTER_UCHAR(DRV_GLOBAL_BASE + DMA_INTERRUPT_FLG_OFFSET + ch, (UCHAR)0);
		WRITE_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET,
			READ_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET) | ((ULONG)1 << ch));
	}
        break;

    case SYSINTR_DU:
        WRITE_REGISTER_ULONG(INTC2MSKCR, INTC2MSKCR_DU);		// DU Interrupt Mask Clear
        break;

    case SYSINTR_VIN:
        WRITE_REGISTER_ULONG(INTC2MSKCR, INTC2MSKCR_VIN);		// VIN Interrupt Mask Clear
        break;

    case SYSINTR_IR:							// IrDA or REMOCON (SCIF3)
		WRITE_REGISTER_USHORT(SCIF3_REGBASE+SCIF_SCSCR_OFFSET,
			READ_REGISTER_USHORT(SCIF3_REGBASE+SCIF_SCSCR_OFFSET) | 0x004c);
		WRITE_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET,
			READ_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET) | (1<<CH_RX_SCIF3));

        break;

    case SYSINTR_USB:
        WRITE_REGISTER_ULONG(INTC2MSKCR, INTC2MSKCR_USB);		// USB Interrupt Mask Clear
        break;

    case SYSINTR_ATAPI:
        WRITE_REGISTER_ULONG(INTC2MSKCR, INTC2MSKCR_ATAPI);		// ATAPI Interrupt Mask Clear
        break;

    case SYSINTR_2DG:
        WRITE_REGISTER_ULONG(INTC2MSKCR, INTC2MSKCR_2D);		// 2D Interrupt Mask Clear
        break;

    case SYSINTR_3DG:
    case SYSINTR_3DG_DMAC:
        WRITE_REGISTER_ULONG(INTC2MSKCR, INTC2MSKCR_3D);		// 3D Interrupt Mask Clear
        break;

    case SYSINTR_SCIF0:							// ProductSerial (SCIF0)
//        WRITE_REGISTER_ULONG(INTC2MSKCR, INTC2MSKCR_SCIF);		// SCIF0-9 Interrupt Mask Clear
		WRITE_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET,
			READ_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET) | (1<<CH_RX_SCIF0));
		WRITE_REGISTER_USHORT(SCIF0_REGBASE+SCIF_SCSCR_OFFSET,
			READ_REGISTER_USHORT(SCIF0_REGBASE+SCIF_SCSCR_OFFSET) | 0x004c);

        break;

    case SYSINTR_ADC:							// ProductSerial (SCIF0)
        WRITE_REGISTER_ULONG(INTC2MSKCR, (INTC2MSKCR_ADC |
                                          INTC2MSKCR_ADCIF));		// SCIF0-9 Interrupt Mask Clear
        break;

    default:
        break;
    }
    INTERRUPTS_ON();
}

//------------------------------------------------------------------------------