oem.c

WinCE5.0BSP for Renesas SH7770

//
//  Copyright(C) Renesas Technology Corp. 1998-2005. All rights reserved.
//
//  OAL Interrupt Handler Library for ITS-DS7
//
//  FILE      : oem.c
//  CREATED   : 2005.08.10
//  MODIFIED  : 2005.11.14
//  AUTHOR    : Renesas Technology Corp.
//  HARDWARE  : RENESAS ITS-DS7
//  HISTORY   :
//              2005.08.10
//              - Created release code.
//                (based on SMDK2410/MAINSTONEII for WCE5.0)
//              2005.11.14
//              - Added support for SYSINTR_3DG_DMAC.

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
//  File: oem.c
//
//  This file implements a standard implementation of OEMInterrupt functions
//  relating to enabling, disabling and finishing interrupts.
//
#include <windows.h>
#include <nkintr.h>
#include <oal.h>
#include "bsp_cfg.h"
#include "platform.h"
#include "sh7770.h"
#include "oalintr.h"
#include "drv_glob.h"
#include "dma.h"

#define SCIF_SCR_REIE		0x0008	// Receive Error Interrupt Enable
#define SCIF_SCR_TOIE		0x0004	// Timeout Interrupt Enable

//------------------------------------------------------------------------------
//
//  Function:  OEMInterruptEnable
//
//  This function enables the IRQ given its corresponding SysIntr value.
//  Function returns true if SysIntr is valid, else false.
//
BOOL OEMInterruptEnable(DWORD sysIntr, LPVOID pvData, DWORD cbData)
{

    BOOL bRet = TRUE;
    int		index, ch;

//    RETAILMSG(1,(TEXT("+OEMInterruptEnable(%d)\r\n"),sysIntr));

#ifdef IMGSHAREETH
    if(sysIntr == SYSINTR_VMINI)
    {
        RETAILMSG(1,
		 (TEXT("Accepting VMini interrupt enable request.\r\n")));
        return (TRUE);
    }
#endif

    INTERRUPTS_OFF();

    switch (sysIntr) {

    case SYSINTR_BREAK:
        break;

    case SYSINTR_RTC_ALARM:
        break;

    case SYSINTR_TIMING:
        break;

    case SYSINTR_ETHER:
        WRITE_REGISTER_ULONG(INTC_INTMSKCLR0, INTC_INTMSKCLR0_IC00);	// IRQ0 Interrupt Mask Clear
		WRITE_REGISTER_USHORT(SF_IRQ0MR, READ_REGISTER_USHORT(SF_IRQ0MR) & ~SF_IRQ0MR_LAN);		// IRQ0 Interrupts mask clear (LAN)
        break;

    case SYSINTR_PCMCIA_STATE:
        WRITE_REGISTER_ULONG(INTC_INTMSKCLR0, INTC_INTMSKCLR0_IC00);	// IRQ0 Interrupt Mask Clear
		WRITE_REGISTER_USHORT(SF_IRQ0MR, READ_REGISTER_USHORT(SF_IRQ0MR) & ~(SF_IRQ0MR_PCC0|SF_IRQ0MR_PCC1));		// IRQ0 Interrupts mask clear (PCC0/PCC1)
        break;

    case SYSINTR_PCMCIA_LEVEL:
        WRITE_REGISTER_ULONG(INTC_INTMSKCLR0, INTC_INTMSKCLR0_IC00);	// IRQ0 Interrupt Mask Clear
		WRITE_REGISTER_USHORT(SF_IRQ0MR, READ_REGISTER_USHORT(SF_IRQ0MR) & ~(SF_IRQ0MR_PCC0));		// IRQ0 Interrupts mask clear (PCC0)
        break;

    case SYSINTR_PCMCIA_LEVEL_1:
        WRITE_REGISTER_ULONG(INTC_INTMSKCLR0, INTC_INTMSKCLR0_IC00);	// IRQ0 Interrupt Mask Clear
		WRITE_REGISTER_USHORT(SF_IRQ0MR, READ_REGISTER_USHORT(SF_IRQ0MR) & ~(SF_IRQ0MR_PCC1));		// IRQ0 Interrupts mask clear (PCC1)
        break;

    case SYSINTR_GPIO:
        WRITE_REGISTER_ULONG(INTC2MSKCR, INTC2MSKCR_GPIO);		// GPIO Interrupt Mask Clear
        break;

    case SYSINTR_HAC:
		index = READ_REGISTER_ULONG(DRV_GLOBAL_BASE + AUD_INDEX_HAC_OFFSET);
		ch    = READ_REGISTER_ULONG(DRV_GLOBAL_BASE + (sizeof(AUDIO_GLOBALS) * index) + PLAY_CH_OFFSET);
		WRITE_REGISTER_UCHAR(DRV_GLOBAL_BASE + DMA_INTERRUPT_FLG_OFFSET + ch, (UCHAR)0);
		WRITE_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET,
			READ_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET) | ((ULONG)1 << ch));

		ch    = READ_REGISTER_ULONG(DRV_GLOBAL_BASE + (sizeof(AUDIO_GLOBALS) * index) + REC_CH_OFFSET);
		WRITE_REGISTER_UCHAR(DRV_GLOBAL_BASE + DMA_INTERRUPT_FLG_OFFSET + ch, (UCHAR)0);
		WRITE_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET,
			READ_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET) | ((ULONG)1 << ch));
        break;

    case SYSINTR_HSPDIF:
        WRITE_REGISTER_ULONG(INTC2MSKCR, INTC2MSKCR_HSPDIF);		// HSPDIF Interrupt Mask Clear
        break;

    case SYSINTR_I2C:
    	WRITE_REGISTER_ULONG(INTC2MSKCR, INTC2MSKCR_I2C);		// I2C Interrupt Mask Clear
        break;

    case SYSINTR_HSSI1:
        WRITE_REGISTER_ULONG(INTC2MSKCR, INTC2MSKCR_HSSI);		// HSSI Interrupt Mask Clear
        break;

    case SYSINTR_HSSI2:
        WRITE_REGISTER_ULONG(INTC2MSKCR, INTC2MSKCR_HSSI);		// HSSI Interrupt Mask Clear
        break;

    case SYSINTR_SRC:
        WRITE_REGISTER_ULONG(INTC2MSKCR, INTC2MSKCR_SRC);		// SRC Interrupt Mask Clear
        break;

    case SYSINTR_DU:
        WRITE_REGISTER_ULONG(INTC2MSKCR, INTC2MSKCR_DU);		// DU Interrupt Mask Clear
        break;

    case SYSINTR_VIN:
        WRITE_REGISTER_ULONG(INTC2MSKCR, INTC2MSKCR_VIN);		// VIN Interrupt Mask Clear
        break;

    case SYSINTR_IR:							// IrDA or REMOCON (SCIF3)
		WRITE_REGISTER_UCHAR(DRV_GLOBAL_BASE + DMA_INTERRUPT_FLG_OFFSET + CH_TX_SCIF3, (UCHAR)0);
		WRITE_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET,
			READ_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET) | ((ULONG)1 << CH_TX_SCIF3));

		WRITE_REGISTER_UCHAR(DRV_GLOBAL_BASE + DMA_INTERRUPT_FLG_OFFSET + CH_RX_SCIF3, (UCHAR)0);
		WRITE_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET,
			READ_REGISTER_ULONG(SH7770_DMAC_REGBASE+DMAC_DINTMR_OFFSET) | ((ULONG)1 << CH_RX_SCIF3));

		WRITE_REGISTER_USHORT(SCIF3_REGBASE+SCIF_SCSCR_OFFSET, 
				READ_REGISTER_USHORT(SCIF3_REGBASE+SCIF_SCSCR_OFFSET) & ~(SCIF_SCR_REIE | SCIF_SCR_TOIE));
        break;

    case SYSINTR_USB:
        WRITE_REGISTER_ULONG(INTC2MSKCR, INTC2MSKCR_USB);		// USB Interrupt Mask Clear
        break;

    case SYSINTR_ATAPI:
        WRITE_REGISTER_ULONG(INTC2MSKCR, INTC2MSKCR_ATAPI);		// ATAPI Interrupt Mask Clear
        break;

    case SYSINTR_2DG:
        WRITE_REGISTER_ULONG(INTC2MSKCR, INTC2MSKCR_2D);		// 2D Interrupt Mask Clear
        break;

    case SYSINTR_3DG:
    case SYSINTR_3DG_DMAC:
        WRITE_REGISTER_ULONG(INTC2MSKCR, INTC2MSKCR_3D);		// 3D Interrupt Mask Clear
        break;

    case SYSINTR_SCIF0:							// ProductSerial (SCIF0)
        WRITE_REGISTER_ULONG(INTC2MSKCR, INTC2MSKCR_SCIF);		// SCIF0-9 Interrupt Mask Clear
        break;

    case SYSINTR_ADC:							// ProductSerial (SCIF0)
        WRITE_REGISTER_ULONG(INTC2MSKCR, (INTC2MSKCR_ADC |
                                          INTC2MSKCR_ADCIF));		// SCIF0-9 Interrupt Mask Clear
        break;

    default:
        bRet = FALSE;   /* don't know about this interrupt value */
        break;
    }

    INTERRUPTS_ON();
    return bRet;
}

//------------------------------------------------------------------------------
//
//  Function:  OEMInterruptDisable(DWORD sysIntr)
//
//  This function disables the IRQ given its corresponding SysIntr value.
//
//
VOID OEMInterruptDisable(DWORD sysIntr)
{

#ifdef DEBUG
//    lpWriteDebugStringFunc(TEXT("OEMInterruptDisable\r\n"));
#endif

    INTERRUPTS_OFF();

    switch	(sysIntr) {

    case SYSINTR_BREAK:
        break;

    case SYSINTR_RTC_ALARM:
        break;

    case SYSINTR_TIMING:
        break;

    case SYSINTR_ETHER:
//     	WRITE_REGISTER_ULONG(INTC_INTMSK0, INTC_INTMSK0_IM00);		// IRQ0 Interrupts mask
		WRITE_REGISTER_USHORT(SF_IRQ0MR, READ_REGISTER_USHORT(SF_IRQ0MR) | SF_IRQ0MR_LAN);		// IRQ0 Interrupts mask(LAN)
        break;

    case SYSINTR_PCMCIA_STATE:
		WRITE_REGISTER_USHORT(SF_IRQ0MR, READ_REGISTER_USHORT(SF_IRQ0MR) | (SF_IRQ0MR_PCC0|SF_IRQ0MR_PCC1));		// IRQ0 Interrupts mask (PCC0/PCC1)
        break;

    case SYSINTR_PCMCIA_LEVEL:
		WRITE_REGISTER_USHORT(SF_IRQ0MR, READ_REGISTER_USHORT(SF_IRQ0MR) | (SF_IRQ0MR_PCC0));		// IRQ0 Interrupts mask (PCC0)
        break;

    case SYSINTR_PCMCIA_LEVEL_1:
		WRITE_REGISTER_USHORT(SF_IRQ0MR, READ_REGISTER_USHORT(SF_IRQ0MR) | (SF_IRQ0MR_PCC1));		// IRQ0 Interrupts mask (PCC1)
        break;