intr.c

WinCE5.0BSP for Renesas SH7770

//
//  Copyright(C) Renesas Technology Corp. 1998-2005. All rights reserved.
//
//  OAL Interrupt Handler Library for ITS-DS7
//
//  FILE      : intr.c
//  CREATED   : 2005.08.10
//  MODIFIED  : 2005.11.14
//  AUTHOR    : Renesas Technology Corp.
//  HARDWARE  : RENESAS ITS-DS7
//  HISTORY   :
//              2005.08.10
//              - Created release code.
//                (based on SMDK2410/MAINSTONEII for WCE5.0)
//              2005.11.14
//              - Added support for 3D DMAC ISR.

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
//  File: intr.c
//
//  This file implement major part of interrupt module for S3C3210X SoC.
//
#include <windows.h>
#include <ceddk.h>
#include <nkintr.h>
#include <oal.h>
#include <oalintr.h>
#include "its_ds7.h"
#include "sh7770.h"

#define DEBUG 1

extern BYTE IntrPrio[];

extern int FPGA_ISR();					// ISR (FPGA)
extern int GPIO_ISR();					// ISR (GPIO)
extern int HAC_ISR0();					// ISR (HAC,BusbridgeDMAC ch0,1)
extern int HAC_ISR1();					// ISR (HAC,BusbridgeDMAC ch0,1)
extern int HAC_ISR2();					// ISR (HAC,BusbridgeDMAC ch0,1)
extern int HSSI_ISR0();					// ISR (HSSI,BusbridgeDMAC ch4,5,6)
extern int HSSI_ISR1();					// ISR (HSSI,BusbridgeDMAC ch4,5,6)
extern int HSSI_ISR2();					// ISR (HSSI,BusbridgeDMAC ch4,5,6)
extern int HSSI_ISR3();					// ISR (HSSI,BusbridgeDMAC ch4,5,6)
extern int HSSI_ISR4();					// ISR (HSSI,BusbridgeDMAC ch4,5,6)
extern int HSPDIF_ISR0();				// ISR (HSPDIF,BusbridgeDMAC ch2,3)
extern int HSPDIF_ISR1();				// ISR (HSPDIF,BusbridgeDMAC ch2,3)
extern int HSPDIF_ISR2();				// ISR (HSPDIF,BusbridgeDMAC ch2,3)
extern int I2C_ISR();					// ISR (I2C)
extern int SRC_ISR0();					// ISR (SRC,BusbridgeDMAC ch7)
extern int SRC_ISR1();					// ISR (SRC,BusbridgeDMAC ch7)
extern int SRC_ISR2();					// ISR (SRC,BusbridgeDMAC ch7)
extern int DU_ISR();					// ISR (DU)
extern int VIN_ISR();					// ISR (VIN)
extern int IR_ISR0();					// ISR (SCIF3,BusbridgeDMAC ch15,16)
extern int IR_ISR1();					// ISR (SCIF3,BusbridgeDMAC ch15,16)
extern int IR_ISR2();					// ISR (SCIF3,BusbridgeDMAC ch15,16)
extern int USB_ISR();					// ISR (USB Host/Func)
extern int ATAPI_ISR();					// ISR (ATAPI)
extern int _2D_ISR();					// ISR (2DG)
extern int _3D_ISR();					// ISR (3DG MBX)
extern int _3D_DMAC_ISR();				// ISR (3DG DMAC)
extern int SCIF_ISR0();					// ISR (SCIF0,BusbridgeDMAC ch11,12)
extern int SCIF_ISR1();					// ISR (SCIF0,BusbridgeDMAC ch11,12)
extern int SCIF_ISR2();					// ISR (SCIF0,BusbridgeDMAC ch11,12)
extern int ADC_ISR1();					// ISR (ADC)
extern int ADC_ISR2();					// ISR (ADC)

//------------------------------------------------------------------------------
//
//  Function:  OALIntrInit
//
//  This function initialize interrupt mapping, hardware and call platform
//  specific initialization.
//
BOOL OALIntrInit()
{
    BOOL rc = FALSE;
    
    OALMSG( OAL_FUNC&&OAL_INTR, (L"+OALInterruptInit\r\n") );

    // Initialize interrupt mapping
    OALIntrMapInit();

#ifdef DEBUG
	lpWriteDebugStringFunc(TEXT("Set Interrupt Level Control Register.\r\n"));
#endif

#ifdef DEBUG
    NKDbgPrintfW(L"INTC_ICR0  =0x%08x\r\n", READ_REGISTER_ULONG(INTC_ICR0));
    NKDbgPrintfW(L"INTC_ICR1  =0x%08x\r\n", READ_REGISTER_ULONG(INTC_ICR1));
    NKDbgPrintfW(L"INTC_INTPRI=0x%08x\r\n", READ_REGISTER_ULONG(INTC_INTPRI));
#endif

    // INTC ICR0 
    WRITE_REGISTER_ULONG(INTC_ICR0, (INTC_ICR0_IRLM0 |		// IRQ3-0:Independent interrupts
                                     INTC_ICR0_IRLM1));		// IRQ4-5:Independent interrupts
								// Others:default value,a0
//    // INTC ICR1 
//    WRITE_REGISTER_ULONG(INTC_ICR1,  INTC_ICR1_IRQ0_RISING);	// IRQ0 Sense select:Rising Edge
//                                                                // IRQ1-5 Sense select:Falling Edge(Default)
    // INTC ICR1 
    WRITE_REGISTER_ULONG(INTC_ICR1,  INTC_ICR1_IRQ0_FALLING);	// IRQ0 Sense select:Falling Edge
                                                                // IRQ1-5 Sense select:Falling Edge(Default)

    // INTC INTPRI
    WRITE_REGISTER_ULONG(INTC_INTPRI,  INTC_INTPRI_IP02);	// IRQ0 Independent interrupts level:2
                                                                // IRQ1-5 Independent interrupts level:0(Default)

#ifdef DEBUG
    NKDbgPrintfW(L"INTC_ICR0  =0x%08x\r\n", READ_REGISTER_ULONG(INTC_ICR0));
    NKDbgPrintfW(L"INTC_ICR1  =0x%08x\r\n", READ_REGISTER_ULONG(INTC_ICR1));
    NKDbgPrintfW(L"INTC_INTPRI=0x%08x\r\n", READ_REGISTER_ULONG(INTC_INTPRI));
#endif

    // INTC2PRI0-13
    WRITE_REGISTER_ULONG(INTC2PRI0, (INTC2PRI0_GPIO   | INTC2PRI0_TMU00  | INTC2PRI0_WDT    | INTC2PRI0_HAC));
    WRITE_REGISTER_ULONG(INTC2PRI1, (INTC2PRI1_MOST   | INTC2PRI1_HSPDIF | INTC2PRI1_HUDI   | INTC2PRI1_I2C));
    WRITE_REGISTER_ULONG(INTC2PRI2, (INTC2PRI2_SHWYDMAC | INTC2PRI2_HSSI | INTC2PRI2_SRC    | INTC2PRI2_DU));
    WRITE_REGISTER_ULONG(INTC2PRI3, (INTC2PRI3_VIN    | INTC2PRI3_REMOCON| INTC2PRI3_YUV    | INTC2PRI3_USB));
    WRITE_REGISTER_ULONG(INTC2PRI4, (INTC2PRI4_ATAPI  | INTC2PRI4_HCAN   | INTC2PRI4_GPS    | INTC2PRI4_2D));
    WRITE_REGISTER_ULONG(INTC2PRI5, (INTC2PRI5_RESERVE| INTC2PRI5_3D     | INTC2PRI5_EXBUSATA | INTC2PRI5_HSPI));
    WRITE_REGISTER_ULONG(INTC2PRI6, (INTC2PRI6_SCIF1_4| INTC2PRI6_SCIF5_7| INTC2PRI6_SCIF089 | INTC2PRI6_ADCIF));
    WRITE_REGISTER_ULONG(INTC2PRI7, (INTC2PRI7_ADC    | INTC2PRI7_5LINE  | INTC2PRI7_PULSE  | INTC2PRI7_BUSDMAC0_3));
    WRITE_REGISTER_ULONG(INTC2PRI8, (INTC2PRI8_BUSDMAC4_7   | INTC2PRI8_BUSDMAC8_10 |
                                     INTC2PRI8_BUSDMAC11_14 | INTC2PRI8_BUSDMAC15_18));
    WRITE_REGISTER_ULONG(INTC2PRI9, (INTC2PRI9_BUSDMAC19_22 | INTC2PRI9_BUSDMAC23_26 |
                                     INTC2PRI9_BUSDMAC27 | INTC2PRI9_BUSDMAC28));
    WRITE_REGISTER_ULONG(INTC2PRI10,(INTC2PRI10_BUSDMAC29   | INTC2PRI10_BUSDMAC30 | INTC2PRI10_BUSDMAC31));
    WRITE_REGISTER_ULONG(INTC2PRI11,(INTC2PRI11_TMU01 | INTC2PRI11_TMU02 | INTC2PRI11_TMU02IC | INTC2PRI11_TMU10));
    WRITE_REGISTER_ULONG(INTC2PRI12,(INTC2PRI12_TMU11 | INTC2PRI12_TMU12 | INTC2PRI12_TMU12IC | INTC2PRI12_TMU20));
    WRITE_REGISTER_ULONG(INTC2PRI13,(INTC2PRI13_TMU21 | INTC2PRI13_TMU22));

	// FPGA (IRQ0:LAN/PCMCIA) Mask Clear
	WRITE_REGISTER_USHORT(SF_IRQ0MR, READ_REGISTER_USHORT(SF_IRQ0MR) & ~(SF_IRQ0MR_LAN|SF_IRQ0MR_PCC0|SF_IRQ0MR_PCC1));

	// BusBridge-DMAC Interrupts Mask Clear
	WRITE_REGISTER_ULONG(INTC2MSKCR, INTC2MSKCR_BUSDMAC);

#ifdef DEBUG
    NKDbgPrintfW(L"INTC2PRI0 =0x%08x\r\n", READ_REGISTER_ULONG(INTC2PRI0));
    NKDbgPrintfW(L"INTC2PRI1 =0x%08x\r\n", READ_REGISTER_ULONG(INTC2PRI1));
    NKDbgPrintfW(L"INTC2PRI2 =0x%08x\r\n", READ_REGISTER_ULONG(INTC2PRI2));
    NKDbgPrintfW(L"INTC2PRI3 =0x%08x\r\n", READ_REGISTER_ULONG(INTC2PRI3));
    NKDbgPrintfW(L"INTC2PRI4 =0x%08x\r\n", READ_REGISTER_ULONG(INTC2PRI4));
    NKDbgPrintfW(L"INTC2PRI5 =0x%08x\r\n", READ_REGISTER_ULONG(INTC2PRI5));
    NKDbgPrintfW(L"INTC2PRI6 =0x%08x\r\n", READ_REGISTER_ULONG(INTC2PRI6));
    NKDbgPrintfW(L"INTC2PRI7 =0x%08x\r\n", READ_REGISTER_ULONG(INTC2PRI7));
    NKDbgPrintfW(L"INTC2PRI8 =0x%08x\r\n", READ_REGISTER_ULONG(INTC2PRI8));
    NKDbgPrintfW(L"INTC2PRI9 =0x%08x\r\n", READ_REGISTER_ULONG(INTC2PRI9));
    NKDbgPrintfW(L"INTC2PRI10=0x%08x\r\n", READ_REGISTER_ULONG(INTC2PRI10));
    NKDbgPrintfW(L"INTC2PRI11=0x%08x\r\n", READ_REGISTER_ULONG(INTC2PRI11));
    NKDbgPrintfW(L"INTC2PRI12=0x%08x\r\n", READ_REGISTER_ULONG(INTC2PRI12));
    NKDbgPrintfW(L"INTC2PRI13=0x%08x\r\n", READ_REGISTER_ULONG(INTC2PRI13));
    lpWriteDebugStringFunc(TEXT("Interrupt Level Control Register setup done.\r\n"));
#endif
#ifdef DEBUG
    lpWriteDebugStringFunc(TEXT("Set Interrupt Mask Register.\r\n"));
#endif

    // All interrupts masked 
//    WRITE_REGISTER_ULONG(INTC2MSKRG, 0xffffffff);		// INTC2 Interrupts mask
//    WRITE_REGISTER_ULONG(INTC_INTMSK0, INTC_INTMSK0_IM00);	// IRQ0(FPGA) Interrupts mask

//    WRITE_REGISTER_ULONG(INTC_USERIMASK, INTC_USERIMASK_WKEY | INTC_USERIMASK_UIMASKF);	// INTC USERIMASK Setting
 
#ifdef DEBUG
    NKDbgPrintfW(L"INTC2MSKRG  =0x%08x\r\n", READ_REGISTER_ULONG(INTC2MSKRG));
    NKDbgPrintfW(L"INTC_INTMSK0=0x%08x\r\n", READ_REGISTER_ULONG(INTC_INTMSK0));
    NKDbgPrintfW(L"INTC2A0     =0x%08x\r\n", READ_REGISTER_ULONG(INTC2A0));
    NKDbgPrintfW(L"INTC2A1     =0x%08x\r\n", READ_REGISTER_ULONG(INTC2A1));
    //NKDbgPrintfW(L"INTC_USERIMASK=%8x\r\n", READ_REGISTER_ULONG(INTC_USERIMASK));
    lpWriteDebugStringFunc(TEXT("mask all interrupts done.\r\n"));
#endif

    /* 
     * Since there are no interrupts enabled in the CPU mask register, there will be 
     * no interrupts generated until they are individually enabled with a call
     * to InterruptEnable().
     */

#ifdef DEBUG
    lpWriteDebugStringFunc(TEXT("Calling HookInterrupt.\r\n"));
#endif

    /*
     * first lets init the Interrupts for the Serial Port
     * if these value are changed, InterruptEnable needs to be changed too */

    HookInterrupt((0x240 - 0x200) / 0x20, FPGA_ISR);	// FPGA (ETHER/PCMCIA)
    IntrPrio[(0x240 - 0x200) / 0x20] = 2;

    HookInterrupt((0x3E0 - 0x200) / 0x20, GPIO_ISR);	// GPIO
    IntrPrio[(0x3E0 - 0x200) / 0x20] = 2;

    HookInterrupt((0x580 - 0x200) / 0x20, HAC_ISR0);	// HAC
    IntrPrio[(0x580 - 0x200) / 0x20] = 14;

    HookInterrupt((0x5E0 - 0x200) / 0x20, HSPDIF_ISR0);	// HSPDIF
    IntrPrio[(0x5E0 - 0x200) / 0x20] = 12;

    HookInterrupt((0x620 - 0x200) / 0x20, I2C_ISR);	// I2C
    IntrPrio[(0x620 - 0x200) / 0x20] = 10;

    HookInterrupt((0x6A0 - 0x200) / 0x20, HSSI_ISR0);	// HSSI ch0 (11.025KHz:OUT)
    IntrPrio[(0x6A0 - 0x200) / 0x20] = 14;