sh7770.inc

WinCE5.0BSP for Renesas SH7770

BSC_ECSPWCRx_EXWT0_ENABLE	.equ	h'00000001	; Ex AREA exwait0 Enable


; Definitions for BSC EXWTSYNC
BSC_EXWTSYNC_SYNC2_DISABLE	.equ	h'00000000	; exwait2 asynchronous  Disable
BSC_EXWTSYNC_SYNC2_ENABLE	.equ	h'00000004	; exwait2 asynchronous  Enable
BSC_EXWTSYNC_SYNC1_DISABLE	.equ	h'00000000	; exwait1 asynchronous  Disable
BSC_EXWTSYNC_SYNC1_ENABLE	.equ	h'00000002	; exwait1 asynchronous  Enable
BSC_EXWTSYNC_SYNC0_DISABLE	.equ	h'00000000	; exwait0 asynchronous  Disable
BSC_EXWTSYNC_SYNC0_ENABLE	.equ	h'00000001	; exwait0 asynchronous  Enable


; Definitions for BSC CS0BSTCTL
BSC_CS0BSTCTL_A0BST_NONE	.equ	h'00000000	; AREA0 BurstROM (No BURST)
BSC_CS0BSTCTL_A0BST_4		.equ	h'00000800	; AREA0 BurstROM (Number of times of burst = 4)
BSC_CS0BSTCTL_A0BST_8		.equ	h'00001000	; AREA0 BurstROM (Number of times of burst = 8)
BSC_CS0BSTCTL_A0BST_16		.equ	h'00001800	; AREA0 BurstROM (Number of times of burst = 16)
BSC_CS0BSTCTL_A0BST_32		.equ	h'00002000	; AREA0 BurstROM (Number of times of burst = 32)



; Definitions for BSC CS0BTPH
BSC_CS0BTPH_A0H_0CYCLE		.equ	h'00000000	; AREA0 BurstROM BurstPitch Hold Cycle  0
BSC_CS0BTPH_A0H_1CYCLE		.equ	h'00000100	; AREA0 BurstROM BurstPitch Hold Cycle  1

BSC_CS0BTPH_A0W_2CYCLE		.equ	h'00000008	; AREA0 BurstROM (BurstPitch of first Cycle = 2)
BSC_CS0BTPH_A0W_3CYCLE		.equ	h'00000018	; AREA0 BurstROM (BurstPitch of first Cycle = 3)
BSC_CS0BTPH_A0W_6CYCLE		.equ	h'00000020	; AREA0 BurstROM (BurstPitch of first Cycle = 6)
BSC_CS0BTPH_A0W_9CYCLE		.equ	h'00000028	; AREA0 BurstROM (BurstPitch of first Cycle = 9)
BSC_CS0BTPH_A0W_12CYCLE		.equ	h'00000030	; AREA0 BurstROM (BurstPitch of first Cycle = 12)
BSC_CS0BTPH_A0W_15CYCLE		.equ	h'00000038	; AREA0 BurstROM (BurstPitch of first Cycle = 15)

BSC_CS0BTPH_A0B_1CYCLE		.equ	h'00000001	; AREA0 BurstROM (BurstPitch of Secont Cycle = 1)
BSC_CS0BTPH_A0B_2CYCLE		.equ	h'00000002	; AREA0 BurstROM (BurstPitch of Secont Cycle = 2)
BSC_CS0BTPH_A0B_3CYCLE		.equ	h'00000003	; AREA0 BurstROM (BurstPitch of Secont Cycle = 3)
BSC_CS0BTPH_A0B_4CYCLE		.equ	h'00000004	; AREA0 BurstROM (BurstPitch of Secont Cycle = 4)
BSC_CS0BTPH_A0B_5CYCLE		.equ	h'00000005	; AREA0 BurstROM (BurstPitch of Secont Cycle = 5)
BSC_CS0BTPH_A0B_6CYCLE		.equ	h'00000006	; AREA0 BurstROM (BurstPitch of Secont Cycle = 6)
BSC_CS0BTPH_A0B_7CYCLE		.equ	h'00000007	; AREA0 BurstROM (BurstPitch of Secont Cycle = 7)



; Definitions for BSC CS1GDST
BSC_CS1GDST_CS1GD_DISABLE		.equ	h'00000000	; AREA1 ACCESS GUARD TIMER SET Disable
BSC_CS1GDST_CS1GD_ENABLE		.equ	h'00000010	; AREA1 ACCESS GUARD TIMER SET Enable

BSC_CS1GDST_TIMER_SET_0CLOCK	.equ	h'00000000	; AREA1 TIMER SET (0 clock)
BSC_CS1GDST_TIMER_SET_1CLOCK	.equ	h'00000001	; AREA1 TIMER SET (1 clock)
BSC_CS1GDST_TIMER_SET_2CLOCK	.equ	h'00000002	; AREA1 TIMER SET (2 clock)
BSC_CS1GDST_TIMER_SET_3CLOCK	.equ	h'00000003	; AREA1 TIMER SET (3 clock)
BSC_CS1GDST_TIMER_SET_4CLOCK	.equ	h'00000004	; AREA1 TIMER SET (4 clock)
BSC_CS1GDST_TIMER_SET_5CLOCK	.equ	h'00000005	; AREA1 TIMER SET (5 clock)
BSC_CS1GDST_TIMER_SET_6CLOCK	.equ	h'00000006	; AREA1 TIMER SET (6 clock)
BSC_CS1GDST_TIMER_SET_7CLOCK	.equ	h'00000007	; AREA1 TIMER SET (7 clock)
BSC_CS1GDST_TIMER_SET_8CLOCK	.equ	h'00000008	; AREA1 TIMER SET (8 clock)
BSC_CS1GDST_TIMER_SET_9CLOCK	.equ	h'00000009	; AREA1 TIMER SET (9 clock)
BSC_CS1GDST_TIMER_SET_10CLOCK	.equ	h'0000000A	; AREA1 TIMER SET (10 clock)
BSC_CS1GDST_TIMER_SET_11CLOCK	.equ	h'0000000B	; AREA1 TIMER SET (11 clock)
BSC_CS1GDST_TIMER_SET_12CLOCK	.equ	h'0000000C	; AREA1 TIMER SET (12 clock)
BSC_CS1GDST_TIMER_SET_13CLOCK	.equ	h'0000000D	; AREA1 TIMER SET (13 clock)
BSC_CS1GDST_TIMER_SET_14CLOCK	.equ	h'0000000E	; AREA1 TIMER SET (14 clock)
BSC_CS1GDST_TIMER_SET_15CLOCK	.equ	h'0000000F	; AREA1 TIMER SET (15 clock)



; Definitions for BSC ECSxGDST
BSC_ECSxGDST_CSxGD_DISABLE		.equ	h'00000000	; External Area ACCESS GUARD TIMER SET Disable
BSC_ECSxGDST_CSxGD_ENABLE		.equ	h'00000010	; External Area ACCESS GUARD TIMER SET Enable

BSC_ECSxGDST_TIMER_SET_0CLOCK	.equ	h'00000000	; External Area TIMER SET (0 clock)
BSC_ECSxGDST_TIMER_SET_1CLOCK	.equ	h'00000001	; External Area TIMER SET (1 clock)
BSC_ECSxGDST_TIMER_SET_2CLOCK	.equ	h'00000002	; External Area TIMER SET (2 clock)
BSC_ECSxGDST_TIMER_SET_3CLOCK	.equ	h'00000003	; External Area TIMER SET (3 clock)
BSC_ECSxGDST_TIMER_SET_4CLOCK	.equ	h'00000004	; External Area TIMER SET (4 clock)
BSC_ECSxGDST_TIMER_SET_5CLOCK	.equ	h'00000005	; External Area TIMER SET (5 clock)
BSC_ECSxGDST_TIMER_SET_6CLOCK	.equ	h'00000006	; External Area TIMER SET (6 clock)
BSC_ECSxGDST_TIMER_SET_7CLOCK	.equ	h'00000007	; External Area TIMER SET (7 clock)
BSC_ECSxGDST_TIMER_SET_8CLOCK	.equ	h'00000008	; External Area TIMER SET (8 clock)
BSC_ECSxGDST_TIMER_SET_9CLOCK	.equ	h'00000009	; External Area TIMER SET (9 clock)
BSC_ECSxGDST_TIMER_SET_10CLOCK	.equ	h'0000000A	; External Area TIMER SET (10 clock)
BSC_ECSxGDST_TIMER_SET_11CLOCK	.equ	h'0000000B	; External Area TIMER SET (11 clock)
BSC_ECSxGDST_TIMER_SET_12CLOCK	.equ	h'0000000C	; External Area TIMER SET (12 clock)
BSC_ECSxGDST_TIMER_SET_13CLOCK	.equ	h'0000000D	; External Area TIMER SET (13 clock)
BSC_ECSxGDST_TIMER_SET_14CLOCK	.equ	h'0000000E	; External Area TIMER SET (14 clock)
BSC_ECSxGDST_TIMER_SET_15CLOCK	.equ	h'0000000F	; External Area TIMER SET (15 clock)



; Definitions for BSC EXDMASETy
BSC_EXDMASETy_DMyECS7_DISABLE	.equ	h'00000000	; External DMA Chanel (Assign to External Area7) No
BSC_EXDMASETy_DMyECS7_ENABLE	.equ	h'00000100	; External DMA Chanel (Assign to External Area7) Yes
BSC_EXDMASETy_DMyECS6_DISABLE	.equ	h'00000000	; External DMA Chanel (Assign to External Area6) No
BSC_EXDMASETy_DMyECS6_ENABLE	.equ	h'00000080	; External DMA Chanel (Assign to External Area6) Yes
BSC_EXDMASETy_DMyECS5_DISABLE	.equ	h'00000000	; External DMA Chanel (Assign to External Area5) No
BSC_EXDMASETy_DMyECS5_ENABLE	.equ	h'00000040	; External DMA Chanel (Assign to External Area5) Yes
BSC_EXDMASETy_DMyECS4_DISABLE	.equ	h'00000000	; External DMA Chanel (Assign to External Area4) No
BSC_EXDMASETy_DMyECS4_ENABLE	.equ	h'00000020	; External DMA Chanel (Assign to External Area4) Yes
BSC_EXDMASETy_DMyECS3_DISABLE	.equ	h'00000000	; External DMA Chanel (Assign to External Area3) No
BSC_EXDMASETy_DMyECS3_ENABLE	.equ	h'00000010	; External DMA Chanel (Assign to External Area3) Yes
BSC_EXDMASETy_DMyECS2_DISABLE	.equ	h'00000000	; External DMA Chanel (Assign to External Area2) No
BSC_EXDMASETy_DMyECS2_ENABLE	.equ	h'00000008	; External DMA Chanel (Assign to External Area2) Yes
BSC_EXDMASETy_DMyECS1_DISABLE	.equ	h'00000000	; External DMA Chanel (Assign to External Area1) No
BSC_EXDMASETy_DMyECS1_ENABLE	.equ	h'00000004	; External DMA Chanel (Assign to External Area1) Yes
BSC_EXDMASETy_DMyECS0_DISABLE	.equ	h'00000000	; External DMA Chanel (Assign to External Area0) No
BSC_EXDMASETy_DMyECS0_ENABLE	.equ	h'00000002	; External DMA Chanel (Assign to External Area0) Yes
BSC_EXDMASETy_DMyCS1_DISABLE	.equ	h'00000000	; External DMA Chanel (Assign to AREA0)          No
BSC_EXDMASETy_DMyCS1_ENABLE		.equ	h'00000001	; External DMA Chanel (Assign to AREA0)          Yes

; Definitions for BSC EXDMASETy
BSC_EXDMCRy_EXDY_DISABLE	.equ	h'00000000	; External DMA Chanel dreqn supoorts asynchronous Disable
BSC_EXDMCRy_EXDY_ENABLE		.equ	h'00000200	; External DMA Chanel dreqn supoorts asynchronous Enable

BSC_EXDMCRy_EXDS_LEVEL		.equ	h'00000000	; External DMA Chanel dreqn Sense Select Low-Level
BSC_EXDMCRy_EXDS_EDGE		.equ	h'00000100	; External DMA Chanel dreqn Sense Select Falling-Edge

BSC_EXDMCRy_EXRS_1CLOCK		.equ	h'00000000	; External DMA Chanel drack Assart Timing 1 Clock
BSC_EXDMCRy_EXRS_2CLOCK		.equ	h'00000020	; External DMA Chanel drack Assart Timing 2 Clock

BSC_EXDMCRy_EXRL_HIGH		.equ	h'00000000	; External DMA Chanel drack Output Select High-Active
BSC_EXDMCRy_EXRL_LOW		.equ	h'00000010	; External DMA Chanel drack Output Select Low-Active

BSC_EXDMCRy_EXAL_HIGH		.equ	h'00000000	; External DMA Chanel dack Output Select High-Active
BSC_EXDMCRy_EXAL_LOW		.equ	h'00000004	; External DMA Chanel dack Output Select Low-Active

BSC_EXDMCRy_EXAC_BOTH		.equ	h'00000000	; External DMA Chanel Assart of signal(Both CS and dack)
BSC_EXDMCRy_EXAC_CS			.equ	h'00000001	; External DMA Chanel Assart of signal(Only CS)
BSC_EXDMCRy_EXAC_DACK		.equ	h'00000002	; External DMA Chanel Assart of signal(Only dack)



; Definitions for BSC BCINTSR
BSC_BCINTSR_ATTE	.equ	h'00000001	; Factor of Interrupts
						; 0:ATA I/F is normal  1:ATA I/F is timeout-error
; Definitions for BSC BCINTCR
BSC_BCINTCR_ATTEC	.equ	h'00000001	; For clearing ATA-Wait-timeout-error
						; 0:Invalid  1:Clear
; Definitions for BSC BCINTMR
BSC_BCINTMR_ATTEM_ENABLE	.equ	h'00000001	; Interrupts of ATA-Wait-timeout-err Enable
BSC_BCINTMR_ATTEM_DISABLE	.equ	h'00000000	; Interrupts of ATA-Wait-timeout-err Disable
						; 0: Disable  1: Enable(output)
; Definitions for BSC EXBATLV
BSC_EXBATLV_EXBLV0_EXT		.equ	h'00000000	; EX_BUS Priority Level0 (External CPU Access)
BSC_EXBATLV_EXBLV0_SHWY		.equ	h'00001000	; EX_BUS Priority Level0 (SuperHyway Access)
BSC_EXBATLV_EXBLV0_EDMAC0	.equ	h'00002000	; EX_BUS Priority Level0 (External DMAC Group0 Access)
BSC_EXBATLV_EXBLV0_EDMAC1	.equ	h'00003000	; EX_BUS Priority Level0 (External DMAC Group1 Access)
BSC_EXBATLV_EXBLV1_EXT		.equ	h'00000000	; EX_BUS Priority Level1 (External CPU Access)
BSC_EXBATLV_EXBLV1_SHWY		.equ	h'00000100	; EX_BUS Priority Level1 (SuperHyway Access)
BSC_EXBATLV_EXBLV1_EDMAC0	.equ	h'00000200	; EX_BUS Priority Level1 (External DMAC Group0 Access)
BSC_EXBATLV_EXBLV1_EDMAC1	.equ	h'00000300	; EX_BUS Priority Level1 (External DMAC Group1 Access)
BSC_EXBATLV_EXBLV2_EXT		.equ	h'00000000	; EX_BUS Priority Level2 (External CPU Access)
BSC_EXBATLV_EXBLV2_SHWY		.equ	h'00000010	; EX_BUS Priority Level2 (SuperHyway Access)
BSC_EXBATLV_EXBLV2_EDMAC0	.equ	h'00000020	; EX_BUS Priority Level2 (External DMAC Group0 Access)
BSC_EXBATLV_EXBLV2_EDMAC1	.equ	h'00000030	; EX_BUS Priority Level2 (External DMAC Group1 Access)
BSC_EXBATLV_EXBLV3_EXT		.equ	h'00000000	; EX_BUS Priority Level3 (External CPU Access)
BSC_EXBATLV_EXBLV3_SHWY		.equ	h'00000001	; EX_BUS Priority Level3 (SuperHyway Access)
BSC_EXBATLV_EXBLV3_EDMAC0	.equ	h'00000002	; EX_BUS Priority Level3 (External DMAC Group0 Access)
BSC_EXBATLV_EXBLV3_EDMAC1	.equ	h'00000003	; EX_BUS Priority Level3 (External DMAC Group1 Access)


;
; for Bus bridge
;     Definitions for DMAC
;
SH7770_DMAC_REGBASE	.equ    (SH7770_BUSBRIDGE_BASE+SH7770_DMAC_OFFSET)
SH7770_DMAC_REGSIZE	.equ    h'00001000

DMAC_DSAR0_OFFSET	.equ	h'00000000
DMAC_DDAR0_OFFSET	.equ	h'00000004
DMAC_DTCR0_OFFSET	.equ	h'00000008
DMAC_DSAR1_OFFSET	.equ	h'0000000C
DMAC_DDAR1_OFFSET	.equ	h'00000010
DMAC_DTCR1_OFFSET	.equ	h'00000014
DMAC_DSASR_OFFSET	.equ	h'00000018
DMAC_DDASR_OFFSET	.equ	h'0000001C
DMAC_DTCSR_OFFSET	.equ	h'00000020
DMAC_DPTR_OFFSET	.equ	h'00000024
DMAC_DCR_OFFSET		.equ	h'00000028
DMAC_DCMDR_OFFSET	.equ	h'0000002C
DMAC_DSTPR_OFFSET	.equ	h'00000030
DMAC_DSTSR_OFFSET	.equ	h'00000034
DMAC_DTIMR_OFFSET	.equ	h'00000800
DMAC_DRMSKR_OFFSET	.equ	h'00000804
DMAC_DMLVLR_OFFSET	.equ	h'00000808
DMAC_DINTSR_OFFSET	.equ	h'0000080C
DMAC_DINTCR_OFFSET	.equ	h'00000810
DMAC_DINTMR_OFFSET	.equ	h'00000814
DMAC_DACTSR_OFFSET	.equ	h'00000818
DMAC_SRSTR0_OFFSET	.equ	h'0000081C
DMAC_SRSTR1_OFFSET	.equ	h'00000820
DMAC_SRSTR2_OFFSET	.equ	h'00000824
DMAC_SRSTR3_OFFSET	.equ	h'00000828
DMAC_SRSTR4_OFFSET	.equ	h'0000082C
DMAC_SRSTR5_OFFSET	.equ	h'00000830
DMAC_SRSTR6_OFFSET	.equ	h'00000834
DMAC_SRSTR7_OFFSET	.equ	h'00000838
DMAC_SRSTR8_OFFSET	.equ	h'0000083C
DMAC_SRSTR9_OFFSET	.equ	h'00000840
DMAC_SRSTR10_OFFSET	.equ	h'00000844
DMAC_SRSTR11_OFFSET	.equ	h'00000848
DMAC_SRSTR12_OFFSET	.equ	h'0000084C
DMAC_SRSTR13_OFFSET	.equ	h'00000850
DMAC_SRSTR14_OFFSET	.equ	h'00000854
DMAC_SRSTR15_OFFSET	.equ	h'00000858
DMAC_SRSTR16_OFFSET	.equ	h'0000085C
DMAC_SRSTR17_OFFSET	.equ	h'00000860
DMAC_SRSTR18_OFFSET	.equ	h'00000864
DMAC_SRSTR19_OFFSET	.equ	h'00000868
DMAC_SRSTR20_OFFSET	.equ	h'0000086C
DMAC_SRSTR21_OFFSET	.equ	h'00000870
DMAC_SRSTR22_OFFSET	.equ	h'00000874
DMAC_SRSTR23_OFFSET	.equ	h'00000878
DMAC_SRSTR24_OFFSET	.equ	h'0000087C
DMAC_SRSTR25_OFFSET	.equ	h'00000880
DMAC_SRSTR26_OFFSET	.equ	h'00000884
DMAC_SRSTR27_OFFSET	.equ	h'00000888
DMAC_SRSTR28_OFFSET	.equ	h'0000088C
DMAC_SRSTR29_OFFSET	.equ	h'00000890
DMAC_SRSTR30_OFFSET	.equ	h'00000894
DMAC_SRSTR31_OFFSET	.equ	h'00000898

;
; for Internal IP
;     Definitions for YUV
;
YUV_REGBASE		.equ    (SH7770_BUSBRIDGE_BASE+SH7770_YUV_OFFSET)
YUV_REGSIZE		.equ    h'00001000

;
; for Internal IP
;     Definitions for VIN
;
VIN_REGBASE		.equ    (SH7770_BUSBRIDGE_BASE+SH7770_VIN_OFFSET)
VIN_REGSIZE		.equ    h'00001000

;
; for Internal IP
;     Definitions for ATAPI
;
ATAPI_REGBASE           .equ    (SH7770_BUSBRIDGE_BASE+SH7770_ATAPI_OFFSET)
ATAPI_REGSIZE           .equ    h'00001000

;
; for Internal IP
;     Definitions for USB Host
;
USBHOST_REGBASE		.equ    (SH7770_BUSBRIDGE_BASE+SH7770_USBHOST_OFFSET)
USBHOST_REGSIZE		.equ    h'00001000

;
; for Internal IP
;     Definitions for USB Function
;
USBFUNC_REGBASE         .equ    (SH7770_BUSBRIDGE_BASE+SH7770_USBFUNC_OFFSET)
USBFUNC_REGSIZE         .equ    h'00001000

;
; for Internal IP
;     Definitions for SPDIF
;
SPDIF_REGBASE           .equ    (SH7770_BUSBRIDGE_BASE+SH7770_SPDIF_OFFSET)
SPDIF_REGSIZE           .equ    h'00001000

;
; for Internal IP
;     Definitions for HAC
;
HAC_REGBASE			.equ    (SH7770_BUSBRIDGE_BASE+SH7770_HAC_OFFSET)
HAC_REGSIZE             .equ    h'00001000

;
; for Internal IP
;     Definitions for I2C
;
I2C_REGBASE             .equ    (SH7770_BUSBRIDGE_BASE+SH7770_I2C_OFFSET)
I2C_REGSIZE             .equ    h'00001000

;
; for Internal IP
;     Definitions for HCAN
;
HCAN_REGBASE            .equ    (SH7770_BUSBRIDGE_BASE+SH7770_HCAN_OFFSET)
HCAN