sh7770.h

WinCE5.0BSP for Renesas SH7770

#define	DMAC_DDAR1_OFFSET	0x00000010
#define	DMAC_DTCR1_OFFSET	0x00000014
#define	DMAC_DSASR_OFFSET	0x00000018
#define	DMAC_DDASR_OFFSET	0x0000001C
#define	DMAC_DTCSR_OFFSET	0x00000020
#define	DMAC_DPTR_OFFSET	0x00000024
#define	DMAC_DCR_OFFSET		0x00000028
#define	DMAC_DCMDR_OFFSET	0x0000002C
#define	DMAC_DSTPR_OFFSET	0x00000030
#define	DMAC_DSTSR_OFFSET	0x00000034
#define	DMAC_DTIMR_OFFSET	0x00000800
#define	DMAC_DRMSKR_OFFSET	0x00000804
#define	DMAC_DMLVLR_OFFSET	0x00000808
#define	DMAC_DINTSR_OFFSET	0x0000080C
#define	DMAC_DINTCR_OFFSET	0x00000810
#define	DMAC_DINTMR_OFFSET	0x00000814
#define	DMAC_DACTSR_OFFSET	0x00000818
#define	DMAC_SRSTR0_OFFSET	0x0000081C
#define	DMAC_SRSTR1_OFFSET	0x00000820
#define	DMAC_SRSTR2_OFFSET	0x00000824
#define	DMAC_SRSTR3_OFFSET	0x00000828
#define	DMAC_SRSTR4_OFFSET	0x0000082C
#define	DMAC_SRSTR5_OFFSET	0x00000830
#define	DMAC_SRSTR6_OFFSET	0x00000834
#define	DMAC_SRSTR7_OFFSET	0x00000838
#define	DMAC_SRSTR8_OFFSET	0x0000083C
#define	DMAC_SRSTR9_OFFSET	0x00000840
#define	DMAC_SRSTR10_OFFSET	0x00000844
#define	DMAC_SRSTR11_OFFSET	0x00000848
#define	DMAC_SRSTR12_OFFSET	0x0000084C
#define	DMAC_SRSTR13_OFFSET	0x00000850
#define	DMAC_SRSTR14_OFFSET	0x00000854
#define	DMAC_SRSTR15_OFFSET	0x00000858
#define	DMAC_SRSTR16_OFFSET	0x0000085C
#define	DMAC_SRSTR17_OFFSET	0x00000860
#define	DMAC_SRSTR18_OFFSET	0x00000864
#define	DMAC_SRSTR19_OFFSET	0x00000868
#define	DMAC_SRSTR20_OFFSET	0x0000086C
#define	DMAC_SRSTR21_OFFSET	0x00000870
#define	DMAC_SRSTR22_OFFSET	0x00000874
#define	DMAC_SRSTR23_OFFSET	0x00000878
#define	DMAC_SRSTR24_OFFSET	0x0000087C
#define	DMAC_SRSTR25_OFFSET	0x00000880
#define	DMAC_SRSTR26_OFFSET	0x00000884
#define	DMAC_SRSTR27_OFFSET	0x00000888
#define	DMAC_SRSTR28_OFFSET	0x0000088C
#define	DMAC_SRSTR29_OFFSET	0x00000890
#define	DMAC_SRSTR30_OFFSET	0x00000894
#define	DMAC_SRSTR31_OFFSET	0x00000898

//
// for Internal IP
//     Definitions for YUV
//
#define	YUV_REGBASE		(SH7770_BUSBRIDGE_BASE+SH7770_YUV_OFFSET)
#define	YUV_REGSIZE		0x00001000

//
// for Internal IP
//     Definitions for VIN
//
#define	VIN_REGBASE		(SH7770_BUSBRIDGE_BASE+SH7770_VIN_OFFSET)
#define	VIN_REGSIZE		0x00001000

//
// for Internal IP
//     Definitions for ATAPI
//
#define	ATAPI_REGBASE		(SH7770_BUSBRIDGE_BASE+SH7770_ATAPI_OFFSET)
#define	ATAPI_REGSIZE		0x00001000

//
// for Internal IP
//     Definitions for USB Host
//
#define	USBHOST_REGBASE		(SH7770_BUSBRIDGE_BASE+SH7770_USBHOST_OFFSET)
#define	USBHOST_REGSIZE		0x00001000

//
// for Internal IP
//     Definitions for USB Function
//
#define	USBFUNC_REGBASE         (SH7770_BUSBRIDGE_BASE+SH7770_USBFUNC_OFFSET)
#define	USBFUNC_REGSIZE         0x00001000

//
// for Internal IP
//     Definitions for SPDIF
//
#define	SPDIF_REGBASE		(SH7770_BUSBRIDGE_BASE+SH7770_SPDIF_OFFSET)
#define	SPDIF_REGSIZE		0x00001000

//
// for Internal IP
//     Definitions for HAC
//
#define	HAC_REGBASE		(SH7770_BUSBRIDGE_BASE+SH7770_HAC_OFFSET)
#define	HAC_REGSIZE             0x00001000

//
// for Internal IP
//     Definitions for I2C
//
#define	I2C_REGBASE             (SH7770_BUSBRIDGE_BASE+SH7770_I2C_OFFSET)
#define	I2C_REGSIZE             0x00001000

//
// for Internal IP
//     Definitions for HCAN
//
#define	HCAN_REGBASE            (SH7770_BUSBRIDGE_BASE+SH7770_HCAN_OFFSET)
#define	HCAN_REGSIZE            0x00001000

//
// for Internal IP
//     Definitions for SSI0
//
#define	SSI0_REGBASE            (SH7770_BUSBRIDGE_BASE+SH7770_SSI0_OFFSET)
#define	SSI0_REGSIZE            0x00001000

//
// for Internal IP
//     Definitions for SSI1
//
#define	SSI1_REGBASE            (SH7770_BUSBRIDGE_BASE+SH7770_SSI1_OFFSET)
#define	SSI1_REGSIZE            0x00001000

//
// for Internal IP
//     Definitions for SSI2
//
#define	SSI2_REGBASE            (SH7770_BUSBRIDGE_BASE+SH7770_SSI2_OFFSET)
#define	SSI2_REGSIZE            0x00001000

//
// for Internal IP
//     Definitions for SSI3
//
#define	SSI3_REGBASE            (SH7770_BUSBRIDGE_BASE+SH7770_SSI3_OFFSET)
#define	SSI3_REGSIZE            0x00001000

//
// for Internal IP
//     Definitions for SRC
//
#define	SRC_REGBASE             (SH7770_BUSBRIDGE_BASE+SH7770_SRC_OFFSET)
#define	SRC_REGSIZE             0x00001000

//
// for Internal IP
//     Definitions for SCIF0
//
#define	SCIF0_REGBASE           (SH7770_BUSBRIDGE_BASE+SH7770_SCIF0_OFFSET)
#define	SCIF0_REGSIZE           0x00001000

//
// for Internal IP
//     Definitions for SCIF1
//
#define	SCIF1_REGBASE           (SH7770_BUSBRIDGE_BASE+SH7770_SCIF1_OFFSET)
#define	SCIF1_REGSIZE           0x00001000

//
// for Internal IP
//     Definitions for SCIF2
//
#define	SCIF2_REGBASE           (SH7770_BUSBRIDGE_BASE+SH7770_SCIF2_OFFSET)
#define	SCIF2_REGSIZE           0x00001000

//
// for Internal IP
//     Definitions for SCIF3
//
#define	SCIF3_REGBASE           (SH7770_BUSBRIDGE_BASE+SH7770_SCIF3_OFFSET)
#define	SCIF3_REGSIZE           0x00001000

//
// for Internal IP
//     Definitions for SCIF4
//
#define	SCIF4_REGBASE           (SH7770_BUSBRIDGE_BASE+SH7770_SCIF4_OFFSET)
#define	SCIF4_REGSIZE           0x00001000

//
// for Internal IP
//     Definitions for SCIF5
//
#define	SCIF5_REGBASE           (SH7770_BUSBRIDGE_BASE+SH7770_SCIF5_OFFSET)
#define	SCIF5_REGSIZE           0x00001000

//
// for Internal IP
//     Definitions for SCIF6
//
#define	SCIF6_REGBASE           (SH7770_BUSBRIDGE_BASE+SH7770_SCIF6_OFFSET)
#define	SCIF6_REGSIZE           0x00001000

//
// for Internal IP
//     Definitions for SCIF7
//
#define	SCIF7_REGBASE           (SH7770_BUSBRIDGE_BASE+SH7770_SCIF7_OFFSET)
#define	SCIF7_REGSIZE           0x00001000


//
// for Internal IP
//     Definitions for SCIF8
//
#define	SCIF8_REGBASE           (SH7770_BUSBRIDGE_BASE+SH7770_SCIF8_OFFSET)
#define	SCIF8_REGSIZE           0x00001000

//
// for Internal IP
//     Definitions for SCIF9
//
#define	SCIF9_REGBASE           (SH7770_BUSBRIDGE_BASE+SH7770_SCIF9_OFFSET)
#define	SCIF9_REGSIZE           0x00001000

//
// Serial Communication Interface with FIFO (SCIF) 
//

#define SCIF_SCSMR_OFFSET			0x0000		// Serial Mode Register 
#define	SCIF_SCBRR_OFFSET			0x0004		// Bit rate register 
#define SCIF_SCSCR_OFFSET			0x0008		// Serial Control Register 
#define SCIF_SCFTDR_OFFSET			0x000c		// transmit FIFO data register 
#define	SCIF_SCFSR_OFFSET			0x0010		// Serail Status Register 
#define SCIF_SCFRDR_OFFSET			0x0014		// Receive Data FIFO register 
#define	SCIF_SCFCR_OFFSET			0x0018		// FIFO Control Register 
#define	SCIF_SCFDR_OFFSET			0x001c		// FIFO Data Count set register 
#define	SCIF_SCSPTR_OFFSET			0x0020		// FIFO Data Count set register 
#define	SCIF_SCLSR_OFFSET			0x0024		// FIFO Data Count set register 


//
// for Internal IP
//     Definitions for HSPI0
//
#define	HSPI0_REGBASE           (SH7770_BUSBRIDGE_BASE+SH7770_HSPI0_OFFSET)
#define	HSPI0_REGSIZE           0x00001000

//
// for Internal IP
//     Definitions for HSPI1
//
#define	HSPI1_REGBASE           (SH7770_BUSBRIDGE_BASE+SH7770_HSPI1_OFFSET)
#define	HSPI1_REGSIZE           0x00001000

//
// for Internal IP
//     Definitions for PWM
//
#define	PWM_REGBASE             (SH7770_BUSBRIDGE_BASE+SH7770_PWM_OFFSET)
#define	PWM_REGSIZE             0x00001000

//
// for Internal IP
//     Definitions for REMOCON
//
#define	REMOCON_REGBASE		(SH7770_BUSBRIDGE_BASE+SH7770_REMOCON_OFFSET)
#define	REMOCON_REGSIZE		0x00001000

//
/