sh7770.h

WinCE5.0BSP for Renesas SH7770

#define	BSC_CSWCR_WRPULSE_15		0x000F0000	// write pulse cycle
#define	BSC_CSWCR_WRPULSE_14		0x000E0000
#define	BSC_CSWCR_WRPULSE_13		0x000D0000
#define	BSC_CSWCR_WRPULSE_12		0x000C0000
#define	BSC_CSWCR_WRPULSE_11		0x000B0000
#define	BSC_CSWCR_WRPULSE_10		0x000A0000
#define	BSC_CSWCR_WRPULSE_9		0x00090000
#define	BSC_CSWCR_WRPULSE_8		0x00080000
#define	BSC_CSWCR_WRPULSE_7		0x00070000
#define	BSC_CSWCR_WRPULSE_6		0x00060000
#define	BSC_CSWCR_WRPULSE_5		0x00050000
#define	BSC_CSWCR_WRPULSE_4		0x00040000
#define	BSC_CSWCR_WRPULSE_3		0x00030000
#define	BSC_CSWCR_WRPULSE_2		0x00020000
#define	BSC_CSWCR_WRPULSE_1		0x00010000

#define	BSC_CSWCR_RDSETUP_7		0x00000700	// read CS setup cycle
#define	BSC_CSWCR_RDSETUP_6		0x00000600
#define	BSC_CSWCR_RDSETUP_5		0x00000500
#define	BSC_CSWCR_RDSETUP_4		0x00000400
#define	BSC_CSWCR_RDSETUP_3		0x00000300
#define	BSC_CSWCR_RDSETUP_2		0x00000200
#define	BSC_CSWCR_RDSETUP_1		0x00000100
#define	BSC_CSWCR_RDSETUP_0		0x00000000

#define	BSC_CSWCR_RDHOLD_7		0x00000070	// read CS hold cycle
#define	BSC_CSWCR_RDHOLD_6		0x00000060
#define	BSC_CSWCR_RDHOLD_5		0x00000050
#define	BSC_CSWCR_RDHOLD_4		0x00000040
#define	BSC_CSWCR_RDHOLD_3		0x00000030
#define	BSC_CSWCR_RDHOLD_2		0x00000020
#define	BSC_CSWCR_RDHOLD_1		0x00000010
#define	BSC_CSWCR_RDHOLD_0		0x00000000

#define	BSC_CSWCR_RDPULSE_15		0x0000000F	// read pulse cycle
#define	BSC_CSWCR_RDPULSE_14		0x0000000E
#define	BSC_CSWCR_RDPULSE_13		0x0000000D
#define	BSC_CSWCR_RDPULSE_12		0x0000000C
#define	BSC_CSWCR_RDPULSE_11		0x0000000B
#define	BSC_CSWCR_RDPULSE_10		0x0000000A
#define	BSC_CSWCR_RDPULSE_9		0x00000009
#define	BSC_CSWCR_RDPULSE_8		0x00000008
#define	BSC_CSWCR_RDPULSE_7		0x00000007
#define	BSC_CSWCR_RDPULSE_6		0x00000006
#define	BSC_CSWCR_RDPULSE_5		0x00000005
#define	BSC_CSWCR_RDPULSE_4		0x00000004
#define	BSC_CSWCR_RDPULSE_3		0x00000003
#define	BSC_CSWCR_RDPULSE_2		0x00000002
#define	BSC_CSWCR_RDPULSE_1		0x00000001


// Definitions for BSC CSPWCR0

#define	BSC_CSPWCR0_V_ENABLE		0x00000020	// AREA0 External Wait Control  Enable
#define	BSC_CSPWCR0_V_DISABLE		0x00000000	// AREA0 External Wait Control  Disable

#define	BSC_CSPWCR0_RB_READY		0x00000010	// AREA0 READY/BUSY Logical Setting  READY
#define	BSC_CSPWCR0_RB_BUSY		0x00000000	// AREA0 READY/BUSY Logical Setting  BUSY

#define	BSC_CSPWCR0_WINV_INV		0x00000008	// AREA0 Wait Signal Polarity Reverse
#define	BSC_CSPWCR0_WINV_NORMAL		0x00000000	// AREA0 Wait Signal Polarity Not Reverse

#define	BSC_CSPWCR0_EXWT2_ENABLE	0x00000004	// AREA0 exwait2 Enable
#define	BSC_CSPWCR0_EXWT2_DISABLE	0x00000000	// AREA0 exwait2 Disable

#define	BSC_CSPWCR0_EXWT1_ENABLE	0x00000002	// AREA0 exwait1 Enable
#define	BSC_CSPWCR0_EXWT1_DISABLE	0x00000000	// AREA0 exwait1 Disable

#define	BSC_CSPWCR0_EXWT0_ENABLE	0x00000001	// AREA0 exwait0 Enable
#define	BSC_CSPWCR0_EXWT0_DISABLE	0x00000000	// AREA0 exwait0 Disable

// Definitions for BSC CSPWCR1

#define	BSC_CSPWCR1_V_ENABLE		0x00000020	// AREA1 External Wait Control  Enable
#define	BSC_CSPWCR1_V_DISABLE		0x00000000	// AREA1 External Wait Control  Disable

#define	BSC_CSPWCR1_RB_READY		0x00000010	// AREA1 READY/BUSY Logical Setting  READY
#define	BSC_CSPWCR1_RB_BUSY		0x00000000	// AREA1 READY/BUSY Logical Setting  BUSY

#define	BSC_CSPWCR1_WINV_INV		0x00000008	// AREA1 Wait Signal Polarity Reverse
#define	BSC_CSPWCR1_WINV_NORMAL		0x00000000	// AREA1 Wait Signal Polarity Not Reverse

#define	BSC_CSPWCR1_EXWT2_ENABLE	0x00000004	// AREA1 exwait2 Enable
#define	BSC_CSPWCR1_EXWT2_DISABLE	0x00000000	// AREA1 exwait2 Disable

#define	BSC_CSPWCR1_EXWT1_ENABLE	0x00000002	// AREA1 exwait1 Enable
#define	BSC_CSPWCR1_EXWT1_DISABLE	0x00000000	// AREA1 exwait1 Disable

#define	BSC_CSPWCR1_EXWT0_ENABLE	0x00000001	// AREA1 exwait0 Enable
#define	BSC_CSPWCR1_EXWT0_DISABLE	0x00000000	// AREA1 exwait0 Disable

// Definitions for BSC ECSPWCR

#define	BSC_ECSPWCR_V_ENABLE		0x00000020	// Ex AREA External Wait Control  Enable
#define	BSC_ECSPWCR_V_DISABLE		0x00000000	// Ex AREA External Wait Control  Disable

#define	BSC_ECSPWCR_RB_READY		0x00000010	// Ex AREA READY/BUSY Logical Setting  READY
#define	BSC_ECSPWCR_RB_BUSY		0x00000000	// Ex AREA READY/BUSY Logical Setting  BUSY

#define	BSC_ECSPWCR_WINV_INV		0x00000008	// Ex AREA Wait Signal Polarity Reverse
#define	BSC_ECSPWCR_WINV_NORMAL		0x00000000	// Ex AREA Wait Signal Polarity Not Reverse

#define	BSC_ECSPWCR_EXWT2_ENABLE	0x00000004	// Ex AREA exwait2 Enable
#define	BSC_ECSPWCR_EXWT2_DISABLE	0x00000000	// Ex AREA exwait2 Disable

#define	BSC_ECSPWCR_EXWT1_ENABLE	0x00000002	// Ex AREA exwait1 Enable
#define	BSC_ECSPWCR_EXWT1_DISABLE	0x00000000	// Ex AREA exwait1 Disable

#define	BSC_ECSPWCR_EXWT0_ENABLE	0x00000001	// Ex AREA exwait0 Enable
#define	BSC_ECSPWCR_EXWT0_DISABLE	0x00000000	// Ex AREA exwait0 Disable

// Definitions for BSC EXWTSYNC
#define	BSC_EXWTSYNC_SYNC2_DISABLE	0x00000000	// exwait2 asynchronous  0:Disable 1:Enable
#define	BSC_EXWTSYNC_SYNC2_ENABLE	0x00000004	// exwait2 asynchronous  0:Disable 1:Enable
#define	BSC_EXWTSYNC_SYNC1_DISABLE	0x00000000	// exwait1 asynchronous  0:Disable 1:Enable
#define	BSC_EXWTSYNC_SYNC1_ENABLE	0x00000002	// exwait1 asynchronous  0:Disable 1:Enable
#define	BSC_EXWTSYNC_SYNC0_DISABLE	0x00000000	// exwait0 asynchronous  0:Disable 1:Enable
#define	BSC_EXWTSYNC_SYNC0_ENABLE	0x00000001	// exwait0 asynchronous  0:Disable 1:Enable

// Definitions for BSC CS0BSTCTL
#define	BSC_CS0BSTCTL_A0BST_NONE	0x00000000	// AREA0 BurstROM (No BURST)
#define	BSC_CS0BSTCTL_A0BST_4		0x00000800	// AREA0 BurstROM (Number of times of burst = 4)
#define	BSC_CS0BSTCTL_A0BST_8		0x00001000	// AREA0 BurstROM (Number of times of burst = 8)
#define	BSC_CS0BSTCTL_A0BST_16		0x00001800	// AREA0 BurstROM (Number of times of burst = 16)
#define	BSC_CS0BSTCTL_A0BST_32		0x00002000	// AREA0 BurstROM (Number of times of burst = 32)

// Definitions for BSC CS0BSTPH
#define	BSC_CS0BSTPH_A0H_0CYCLE		0x00000000	// AREA0 BurstROM BurstPitch Hold Cycle  0:0 1:1
#define	BSC_CS0BSTPH_A0H_1CYCLE		0x00000100	// AREA0 BurstROM BurstPitch Hold Cycle  0:0 1:1

#define	BSC_CS0BSTPH_A0W_2CYCLE		0x00000008	// AREA0 BurstROM (BurstPitch of first Cycle = 2)
#define	BSC_CS0BSTPH_A0W_3CYCLE		0x00000018	// AREA0 BurstROM (BurstPitch of first Cycle = 3)
#define	BSC_CS0BSTPH_A0W_6CYCLE		0x00000020	// AREA0 BurstROM (BurstPitch of first Cycle = 6)
#define	BSC_CS0BSTPH_A0W_9CYCLE		0x00000028	// AREA0 BurstROM (BurstPitch of first Cycle = 9)
#define	BSC_CS0BSTPH_A0W_12CYCLE	0x00000030	// AREA0 BurstROM (BurstPitch of first Cycle = 12)
#define	BSC_CS0BSTPH_A0W_15CYCLE	0x00000038	// AREA0 BurstROM (BurstPitch of first Cycle = 15)

#define	BSC_CS0BSTPH_A0B_1CYCLE		0x00000001	// AREA0 BurstROM (BurstPitch of Secont Cycle = 1)
#define	BSC_CS0BSTPH_A0B_2CYCLE		0x00000002	// AREA0 BurstROM (BurstPitch of Secont Cycle = 2)
#define	BSC_CS0BSTPH_A0B_3CYCLE		0x00000003	// AREA0 BurstROM (BurstPitch of Secont Cycle = 3)
#define	BSC_CS0BSTPH_A0B_4CYCLE		0x00000004	// AREA0 BurstROM (BurstPitch of Secont Cycle = 4)
#define	BSC_CS0BSTPH_A0B_5CYCLE		0x00000005	// AREA0 BurstROM (BurstPitch of Secont Cycle = 5)
#define	BSC_CS0BSTPH_A0B_6CYCLE		0x00000006	// AREA0 BurstROM (BurstPitch of Secont Cycle = 6)
#define	BSC_CS0BSTPH_A0B_7CYCLE		0x00000007	// AREA0 BurstROM (BurstPitch of Secont Cycle = 7)

// Definitions for BSC CS1GDST
#define	BSC_CS1GDST_CS1GD_DISABLE	0x00000000	// AREA1 ACCESS GUARD TIMER SET 0:Disable 1:Enable
#define	BSC_CS1GDST_CS1GD_ENABLE	0x00000010	// AREA1 ACCESS GUARD TIMER SET 0:Disable 1:Enable

#define	BSC_CS1GDST_TIMER_SET_0CLOCK	0x00000001	// AREA1 TIMER SET (1 clock)
#define	BSC_CS1GDST_TIMER_SET_1CLOCK	0x00000001	// AREA1 TIMER SET (1 clock)
#define	BSC_CS1GDST_TIMER_SET_2CLOCK	0x00000002	// AREA1 TIMER SET (2 clock)
#define	BSC_CS1GDST_TIMER_SET_3CLOCK	0x00000003	// AREA1 TIMER SET (3 clock)
#define	BSC_CS1GDST_TIMER_SET_4CLOCK	0x00000004	// AREA1 TIMER SET (4 clock)
#define	BSC_CS1GDST_TIMER_SET_5CLOCK	0x00000005	// AREA1 TIMER SET (5 clock)
#define	BSC_CS1GDST_TIMER_SET_6CLOCK	0x00000006	// AREA1 TIMER SET (6 clock)
#define	BSC_CS1GDST_TIMER_SET_7CLOCK	0x00000007	// AREA1 TIMER SET (7 clock)
#define	BSC_CS1GDST_TIMER_SET_8CLOCK	0x00000008	// AREA1 TIMER SET (8 clock)
#define	BSC_CS1GDST_TIMER_SET_9CLOCK	0x00000009	// AREA1 TIMER SET (9 clock)
#define	BSC_CS1GDST_TIMER_SET_10CLOCK	0x0000000A	// AREA1 TIMER SET (10 clock)
#define	BSC_CS1GDST_TIMER_SET_11CLOCK	0x0000000B	// AREA1 TIMER SET (11 clock)
#define	BSC_CS1GDST_TIMER_SET_12CLOCK	0x0000000C	// AREA1 TIMER SET (12 clock)
#define	BSC_CS1GDST_TIMER_SET_13CLOCK	0x0000000D	// AREA1 TIMER SET (13 clock)
#define	BSC_CS1GDST_TIMER_SET_14CLOCK	0x0000000E	// AREA1 TIMER SET (14 clock)
#define	BSC_CS1GDST_TIMER_SET_15CLOCK	0x0000000F	// AREA1 TIMER SET (15 clock)

// Definitions for BSC ECSxGDST
#define	BSC_ECSxGDST_CS1GD_DISABLE		0x00000000	// External Area ACCESS GUARD TIMER SET 0:Disable 1:Enable
#define	BSC_ECSxGDST_CS1GD_ENABLE		0x00000010	// External Area ACCESS GUARD TIMER SET 0:Disable 1:Enable

#define	BSC_ECSxGDST_TIMER_SET_0CLOCK	0x00000000	// External Area TIMER SET (1 clock)
#define	BSC_ECSxGDST_TIMER_SET_1CLOCK	0x00000001	// External Area TIMER SET (1 clock)
#define	BSC_ECSxGDST_TIMER_SET_2CLOCK	0x00000002	// External Area TIMER SET (2 clock)
#define	BSC_ECSxGDST_TIMER_SET_3CLOCK	0x00000003	// External Area TIMER SET (3 clock)
#define	BSC_ECSxGDST_TIMER_SET_4CLOCK	0x00000004	// External Area TIMER SET (4 clock)
#define	BSC_ECSxGDST_TIMER_SET_5CLOCK	0x00000005	// External Area TIMER SET (5 clock)
#define	BSC_ECSxGDST_TIMER_SET_6CLOCK	0x00000006	// External Area TIMER SET (6 clock)
#define	BSC_ECSxGDST_TIMER_SET_7CLOCK	0x00000007	// External Area TIMER SET (7 clock)
#define	BSC_ECSxGDST_TIMER_SET_8CLOCK	0x00000008	// External Area TIMER SET (8 clock)
#define	BSC_ECSxGDST_TIMER_SET_9CLOCK	0x00000009	// External Area TIMER SET (9 clock)
#define	BSC_ECSxGDST_TIMER_SET_10CLOCK	0x0000000A	// External Area TIMER SET (10 clock)
#define	BSC_ECSxGDST_TIMER_SET_11CLOCK	0x0000000B	// External Area TIMER SET (11 clock)
#define	BSC_ECSxGDST_TIMER_SET_12CLOCK	0x0000000C	// External Area TIMER SET (12 clock)
#define	BSC_ECSxGDST_TIMER_SET_13CLOCK	0x0000000D	// External Area TIMER SET (13 clock)
#define	BSC_ECSxGDST_TIMER_SET_14CLOCK	0x0000000E	// External Area TIMER SET (14 clock)
#define	BSC_ECSxGDST_TIMER_SET_15CLOCK	0x0000000F	// External Area TIMER SET (15 clock)

// Definitions for BSC EXDMASETy
#define	BSC_EXDMASETy_DMyECS7_DISABLE		0x00000000	// External DMA Chanel (Assign to External Area7) 0:No 1:Yes
#define	BSC_EXDMASETy_DMyECS7_ENABLE		0x00000100	// External DMA Chanel (Assign to External Area7) 0:No 1:Yes
#define	BSC_EXDMASETy_DMyECS6_DISABLE		0x00000000	// External DMA Chanel (Assign to External Area6) 0:No 1:Yes
#define	BSC_EXDMASETy_DMyECS6_ENABLE		0x00000080	// External DMA Chanel (Assign to External Area6) 0:No 1:Yes
#define	BSC_EXDMASETy_DMyECS5_DISABLE		0x00000000	// External DMA Chanel (Assign to External Area5) 0:No 1:Yes
#define	BSC_EXDMASETy_DMyECS5_ENABLE		0x00000040	// External DMA Chanel (Assign to External Area5) 0:No 1:Yes
#define	BSC_EXDMASETy_DMyECS4_DISABLE		0x00000000	// External DMA Chanel (Assign to External Area4) 0:No 1:Yes
#define	BSC_EXDMASETy_DMyECS4_ENABLE		0x00000020	// External DMA Chanel (Assign to External Area4) 0:No 1:Yes
#define	BSC_EXDMASETy_DMyECS3_DISABLE		0x00000000	// External DMA Chanel (Assign to External Area3) 0:No 1:Yes
#define	BSC_EXDMASETy_DMyECS3_ENABLE		0x00000010	// External DMA Chanel (Assign to External Area3) 0:No 1:Yes
#define	BSC_EXDMASETy_DMyECS2_DISABLE		0x00000000	// External DMA Chanel (Assign to External Area2) 0:No 1:Yes
#define	BSC_EXDMASETy_DMyECS2_ENABLE		0x00000008	// External DMA Chanel (Assign to External Area2) 0:No 1:Yes
#define	BSC_EXDMASETy_DMyECS1_DISABLE		0x00000000	// External DMA Chanel (Assign to External Area1) 0:No 1:Yes
#define	BSC_EXDMASETy_DMyECS1_ENABLE		0x00000004	// External DMA Chanel (Assign to External Area1) 0:No 1:Yes
#define	BSC_EXDMASETy_DMyECS0_DISABLE		0x00000000	// External DMA Chanel (Assign to External Area0) 0:No 1:Yes
#define	BSC_EXDMASETy_DMyECS0_ENABLE		0x00000002	// External DMA Chanel (Assign to External Area0) 0:No 1:Yes
#define	BSC_EXDMASETy_DMyCS1_DISABLE		0x00000000	// External DMA Chanel (Assign to AREA0)          0:No 1:Yes
#define	BSC_EXDMASETy_DMyCS1_ENABLE			0x00000001	// External DMA Chanel (Assign to AREA0)          0:No 1:Yes

// Definitions for BSC EXDMASETy
#define	BSC_EXDMCRy_EXDY_DISABLE	0x00000000	// External DMA Chanel dreqn supoorts asynchronous
#define	BSC_EXDMCRy_EXDY_ENABLE		0x00000200	// External DMA Chanel dreqn supoorts asynchronous

#define	BSC_EXDMCRy_EXDS_LEVEL		0x00000000	// External DMA Chanel dreqn Sense Select
#define	BSC_EXDMCRy_EXDS_EDGE		0x00000100	// External DMA Chanel dreqn Sense Select

#define	BSC_EXDMCRy_EXRS_1CLOCK		0x00000000	// External DMA Chanel drack Assart Timing
#define	BSC_EXDMCRy_EXRS_2CLOCK		0x00000020	// External DMA Chanel drack Assart Timing

#define	BSC_EXDMCRy_EXRL_HIGH		0x00000000	// External DMA Chanel drack Output Select
#define	BSC_EXDMCRy_EXRL_LOW		0x00000010	// External DMA Chanel drack Output Select

#define	BSC_EXDMCRy_EXAL_HIGH		0x00000000	// External DMA Chanel dack Output Select
#define	BSC_EXDMCRy_EXAL_LOW		0x00000004	// External DMA Chanel dack Output Select

#define	BSC_EXDMCRy_EXAC_BOTH		0x00000000	// External DMA Chanel Assart of signal(Both CS and dack)
#define	BSC_EXDMCRy_EXAC_CS			0x00000001	// External DMA Chanel Assart of signal(Only CS)
#define	BSC_EXDMCRy_EXAC_DACK		0x00000002	// External DMA Chanel Assart of signal(Only dack)

// Definitions for BSC BCINTSR
#define	BSC_BCINTSR_ATTE		0x00000001	// Factor of Interrupts
							// 0:ATA I/F is normal  1:ATA I/F is timeout-error
// Definitions for BSC BCINTCR
#define	BSC_BCINTCR_ATTEC		0x00000001	// For clearing ATA-Wait-timeout-error
							// 0:Invalid  1:Clear
// Definitions for BSC BCINTMR
#define	BSC_BCINTMR_ATTEM_ENABLE	0x00000001	// Interrupts of ATA-Wait-timeout-err Enable
#define	BSC_BCINTMR_ATTEM_DISABLE	0x00000000	// Interrupts of ATA-Wait-timeout-err Disable
							// 0: Disable  1: Enable(output)
// Definitions for BSC EXBATLV
#define	BSC_EXBATLV_EXBLV0_EXT		0x00000000	// EX_BUS Priority Level0 (External CPU Access)
#define	BSC_EXBATLV_EXBLV0_SHWY		0x00001000	// EX_BUS Priority Level0 (SuperHyway Access)
#define	BSC_EXBATLV_EXBLV0_EDMAC0	0x00002000	// EX_BUS Priority Level0 (External DMAC Group0 Access)
#define	BSC_EXBATLV_EXBLV0_EDMAC1	0x00003000	// EX_BUS Priority Level0 (External DMAC Group1 Access)
#define	BSC_EXBATLV_EXBLV1_EXT		0x00000000	// EX_BUS Priority Level1 (External CPU Access)
#define	BSC_EXBATLV_EXBLV1_SHWY		0x00000100	// EX_BUS Priority Level1 (SuperHyway Access)
#define	BSC_EXBATLV_EXBLV1_EDMAC0	0x00000200	// EX_BUS Priority Level1 (External DMAC Group0 Access)
#define	BSC_EXBATLV_EXBLV1_EDMAC1	0x00000300	// EX_BUS Priority Level1 (External DMAC Group1 Access)
#define	BSC_EXBATLV_EXBLV2_EXT		0x00000000	// EX_BUS Priority Level2 (External CPU Access)
#define	BSC_EXBATLV_EXBLV2_SHWY		0x00000010	// EX_BUS Priority Level2 (SuperHyway Access)
#define	BSC_EXBATLV_EXBLV2_EDMAC0	0x00000020	// EX_BUS Priority Level2 (External DMAC Group0 Access)
#define	BSC_EXBATLV_EXBLV2_EDMAC1	0x00000030	// EX_BUS Priority Level2 (External DMAC Group1 Access)
#define	BSC_EXBATLV_EXBLV3_EXT		0x00000000	// EX_BUS Priority Level3 (External CPU Access)
#define	BSC_EXBATLV_EXBLV3_SHWY		0x00000001	// EX_BUS Priority Level3 (SuperHyway Access)
#define	BSC_EXBATLV_EXBLV3_EDMAC0	0x00000002	// EX_BUS Priority Level3 (External DMAC Group0 Access)
#define	BSC_EXBATLV_EXBLV3_EDMAC1	0x00000003	// EX_BUS Priority Level3 (External DMAC Group1 Access)

//
// for Bus bridge
//     Definitions for DMAC
//
#define	SH7770_DMAC_REGBASE	(SH7770_BUSBRIDGE_BASE+SH7770_DMAC_OFFSET)
#define	SH7770_DMAC_REGSIZE	0x00001000

#define	DMAC_DSAR0_OFFSET	0x00000000
#define	DMAC_DDAR0_OFFSET	0x00000004
#define	DMAC_DTCR0_OFFSET	0x00000008
#define	DMAC_DSAR1_OFFSET	0x0000000C