sh7770.h

WinCE5.0BSP for Renesas SH7770

// Definitions for VCRSYS PMSR2

#define VCRSYS_PMSR2_SCICK_SCIF		0x00000000	//; SCIF CLK
#define VCRSYS_PMSR2_SCICK_GPIO		0x80000000	//; GPIO

#define VCRSYS_PMSR2_SCIF9_GPIO		0x00000000	//; GPIO
#define VCRSYS_PMSR2_SCIF9_SCIF		0x02000000	//; SCIF9

#define VCRSYS_PMSR2_SCIF7_SCIF		0x00000000	//; SCIF7
#define VCRSYS_PMSR2_SCIF7_HSPI		0x00800000	//; HSPI1
#define VCRSYS_PMSR2_SCIF7_SCK		0x01800000	//; SCK

#define VCRSYS_PMSR2_SCIF6_RX		0x00000000	//; RX6
#define VCRSYS_PMSR2_SCIF6_I2C		0x00400000	//; I2C_SDA

#define VCRSYS_PMSR2_SCIF4_HSPI		0x00000000	//; HSPI0
#define VCRSYS_PMSR2_SCIF4_SCIF		0x00100000	//; SCIF4,5

#define VCRSYS_PMSR2_SCIF3_GPIO		0x00000000	//; GPIO
#define VCRSYS_PMSR2_SCIF3_SCIF		0x00080000	//; SCIF3

#define VCRSYS_PMSR2_SCIF2_GPIO		0x00000000	//; GPIO
#define VCRSYS_PMSR2_SCIF2_SCIF		0x00040000	//; SCIF2

#define VCRSYS_PMSR2_SCIF0_GPIO			0x00000000	//; GPIO
#define VCRSYS_PMSR2_SCIF0_SCIF0_GPIO	0x00010000	//; SCIF0(Tx,Rx), GPIO
#define VCRSYS_PMSR2_SCIF0_SCIF0		0x00020000	//; SCIF0(Tx,Rx,RTS,CTS)
#define VCRSYS_PMSR2_SCIF0_SCIF0_1		0x00030000	//; SCIF0(Tx,Rx), SCIF1(Tx,Rx)

#define VCRSYS_PMSR2_ADOCK_AUDIO	0x00000000	//; AUDIO_CLK
#define VCRSYS_PMSR2_ADOCK_GPIO		0x00008000	//; GPIO

#define VCRSYS_PMSR2_HARES_SSI		0x00000000	//; SSI_WS1
#define VCRSYS_PMSR2_HARES_HAC		0x00004000	//; HAC_RES

#define VCRSYS_PMSR2_SSI23_SSI		0x00000000	//; SSI2,3
#define VCRSYS_PMSR2_SSI23_HAC		0x00001000	//; HAC

#define VCRSYS_PMSR2_SSI1_SSI		0x00000000	//; SSI1
#define VCRSYS_PMSR2_SSI1_GPIO		0x00000800	//; HAC

#define VCRSYS_PMSR2_SSI0_SSI		0x00000000	//; SSI0
#define VCRSYS_PMSR2_SSI0_GPIO		0x00000400	//; GPIO

#define VCRSYS_PMSR2_SPDIF1_GPIO	0x00000000	//; GPIO
#define VCRSYS_PMSR2_SPDIF1_SPDIF	0x00000100	//; SPDIF
#define VCRSYS_PMSR2_SPDIF1_PIO		0x00000200	//; PIO

#define VCRSYS_PMSR2_SPDIF0_GPIO	0x00000000	//; GPIO
#define VCRSYS_PMSR2_SPDIF0_SPDIF	0x00000040	//; SPDIF
#define VCRSYS_PMSR2_SPDIF0_PIO		0x00000080	//; PIO

#define VCRSYS_PMSR2_CDE_CDE		0x00000000	//; CDE
#define VCRSYS_PMSR2_CDE_GPIO		0x00000004	//; GPIO

#define VCRSYS_PMSR2_ODDF_ODDF		0x00000000	//; ODDF
#define VCRSYS_PMSR2_ODDF_GPIO		0x00000002	//; GPIO

// Definitions for VCRSYS PMSR3

#define VCRSYS_PMSR3_REMC_IRREC		0x00000000	//; IRREC
#define VCRSYS_PMSR3_REMC_GPIO		0x00000040	//; GPIO

#define VCRSYS_PMSR3_TIME1_TIMER	0x00000000	//; TIMER0
#define VCRSYS_PMSR3_TIME1_GPIO		0x00000010	//; GPIO

#define VCRSYS_PMSR3_TIME0_TIMER	0x00000000	//; TIMER0
#define VCRSYS_PMSR3_TIME0_PWM		0x00000004	//; PWM0
#define VCRSYS_PMSR3_TIME0_GPIO		0x00000008	//; GPIO

#define VCRSYS_PMSR3_CANB_GPIO		0x00000000	//; GPIO
#define VCRSYS_PMSR3_CANB_HCAN		0x00000002	//; HCAN(CAN_TX,CAN_RX)

#define VCRSYS_PMSR3_CANA_GPIO		0x00000000	//; GPIO
#define VCRSYS_PMSR3_CANA_HCAN		0x00000001	//; HCAN(CAN_ERR)

// Definitions for VCRSYS PMSR4

#define VCRSYS_PMSR4_VID_VIDEOIN		0x00000000	//; VIDEO IN (ITU-R601, ITU-R656)
#define VCRSYS_PMSR4_VID_VIDEOIN_AUD	0x10000000	//; VIDEO IN (ITU-R656), AUD (8bit mode)
#define VCRSYS_PMSR4_VID_DIGITAL_RGB	0x20000000	//; Digital RGB
#define VCRSYS_PMSR4_VID_GPIO			0x30000000	//; GPIO

#define VCRSYS_PMSR4_DAK2_DACK			0x00000000	//; DACK2
#define VCRSYS_PMSR4_DAK2_GPIO			0x00100000	//; GPIO

#define VCRSYS_PMSR4_AUD_GPIO			0x00000000	//; GPIO
#define VCRSYS_PMSR4_AUD_AUD			0x00010000	//; AUD
#define VCRSYS_PMSR4_AUD_DIGITAL_RGB	0x00020000	//; Digital RGB

#define VCRSYS_PMSR4_DISP_DISP			0x00000000	//; DISP
#define VCRSYS_PMSR4_DISP_GPIO			0x00004000	//; GPIO

#define VCRSYS_PMSR4_DCKO_DOTCLK		0x00000000	//; DOTCLKOT
#define VCRSYS_PMSR4_DCKO_GPIO			0x00002000	//; GPIO

#define VCRSYS_PMSR4_SDBUP_SDBUP		0x00000000	//; DISP
#define VCRSYS_PMSR4_SDBUP_GPIO			0x00000004	//; GPIO

#define VCRSYS_PMSR4_SDSELF_SDSELF		0x00000000	//; DISP
#define VCRSYS_PMSR4_SDSELF_GPIO		0x00000002	//; GPIO

#define VCRSYS_PMSR4_RESOUT_RESOUT		0x00000000	//; DISP
#define VCRSYS_PMSR4_RESOUT_GPIO		0x00000001	//; GPIO

// Definitions for VCRSYS PMSRG

#define VCRSYS_PMSRG_A25_EXBUS	0x00000000	//; A25
#define VCRSYS_PMSRG_A25_GPIO	0x02000000	//; GPIO

#define VCRSYS_PMSRG_A24_EXBUS	0x00000000	//; A24
#define VCRSYS_PMSRG_A24_GPIO	0x01000000	//; GPIO

#define VCRSYS_PMSRG_A23_EXBUS	0x00000000	//; A23
#define VCRSYS_PMSRG_A23_GPIO	0x00800000	//; GPIO

#define VCRSYS_PMSRG_A22_EXBUS	0x00000000	//; A22
#define VCRSYS_PMSRG_A22_GPIO	0x00400000	//; GPIO

#define VCRSYS_PMSRG_A21_EXBUS	0x00000000	//; A21
#define VCRSYS_PMSRG_A21_GPIO	0x00200000	//; GPIO

#define VCRSYS_PMSRG_A20_EXBUS	0x00000000	//; A20
#define VCRSYS_PMSRG_A20_GPIO	0x00100000	//; GPIO

#define VCRSYS_PMSRG_A19_EXBUS	0x00000000	//; A19
#define VCRSYS_PMSRG_A19_GPIO	0x00080000	//; GPIO

#define VCRSYS_PMSRG_A18_EXBUS	0x00000000	//; A18
#define VCRSYS_PMSRG_A18_GPIO	0x00040000	//; GPIO

#define VCRSYS_PMSRG_A17_EXBUS	0x00000000	//; A17
#define VCRSYS_PMSRG_A17_GPIO	0x00020000	//; GPIO

#define VCRSYS_PMSRG_A16_EXBUS	0x00000000	//; A16
#define VCRSYS_PMSRG_A16_GPIO	0x00010000	//; GPIO

#define VCRSYS_PMSRG_A15_EXBUS	0x00000000	//; A15
#define VCRSYS_PMSRG_A15_GPIO	0x00008000	//; GPIO

#define VCRSYS_PMSRG_A14_EXBUS	0x00000000	//; A14
#define VCRSYS_PMSRG_A14_GPIO	0x00004000	//; GPIO

#define VCRSYS_PMSRG_A13_EXBUS	0x00000000	//; A13
#define VCRSYS_PMSRG_A13_GPIO	0x00002000	//; GPIO

#define VCRSYS_PMSRG_A12_EXBUS	0x00000000	//; A12
#define VCRSYS_PMSRG_A12_GPIO	0x00001000	//; GPIO

#define VCRSYS_PMSRG_A11_EXBUS	0x00000000	//; A11
#define VCRSYS_PMSRG_A11_GPIO	0x00000800	//; GPIO


// Definitions for VCRSYS DBGSTR
#define	VCRSYS_DBGSTR_DBG		0x00000001	// TBD

// Definitions for VCRSYS DBR(2,3)
#define	VCRSYS_DBR_BME			0x40000000	// Select Target Bus in IOBUS or IOBUS2
#define	VCRSYS_DBR_BMI_ALL		0x00000000	// Select All Bus
#define	VCRSYS_DBR_BMI_HAC		0x00010000	// Select HAC Bus
#define	VCRSYS_DBR_BMI_I2S0		0x00020000	// Select I2S0 Bus
#define	VCRSYS_DBR_BMI_I2S1		0x00030000	// Select I2S1 Bus
#define	VCRSYS_DBR_BMI_I2S2		0x00040000	// Select I2S2 Bus
#define	VCRSYS_DBR_BMI_I2S3		0x00050000	// Select I2S3 Bus
#define	VCRSYS_DBR_BMI_SPDIF	0x00060000	// Select SPDIF Bus
#define	VCRSYS_DBR_BMI_SRC		0x00080000	// Select SRC Bus
#define	VCRSYS_DBR_BMI_SCIF		0x00090000	// Select SCIF Bus
#define	VCRSYS_DBR_BMI_YUV		0x000A0000	// Select YUV Bus
#define	VCRSYS_DBR_BMI_USB		0x000B0000	// Select USB Bus

// Definitions for VCRSYS DRR(2,3)
#define	VCRSYS_DRR_TRE_OFF		0x00000000	// Trace off
#define	VCRSYS_DRR_TRE_ON		0x00000008	// Trace on
#define	VCRSYS_DRR_BIE_OFF		0x00000000	// ASE break request on
#define	VCRSYS_DRR_BIE_ON		0x00000001	// ASE break request off

// Definitions for VCRSYS DCBR(10,11)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ0_READ	0x00000000 << 6	// LEVEL DREQ0(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ0_WRITE	0x00000004 << 6	// LEVEL DREQ0(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ1_READ	0x00000008 << 6	// LEVEL DREQ1(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ1_WRITE	0x0000000C << 6	// LEVEL DREQ1(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ2_READ	0x00000010 << 6	// LEVEL DREQ2(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ2_WRITE	0x00000014 << 6	// LEVEL DREQ2(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ3_READ	0x00000018 << 6	// LEVEL DREQ3(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ3_WRITE	0x0000001C << 6	// LEVEL DREQ3(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ4_READ	0x00000020 << 6	// LEVEL DREQ4(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ4_WRITE	0x00000024 << 6	// LEVEL DREQ4(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ5_READ	0x00000028 << 6	// LEVEL DREQ5(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ5_WRITE	0x0000002C << 6	// LEVEL DREQ5(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ6_READ	0x00000030 << 6	// LEVEL DREQ6(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ6_WRITE	0x00000034 << 6	// LEVEL DREQ6(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ7_READ	0x00000038 << 6	// LEVEL DREQ7(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ7_WRITE	0x0000003C << 6	// LEVEL DREQ7(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ8_READ	0x00000040 << 6	// LEVEL DREQ8(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ8_WRITE	0x00000044 << 6	// LEVEL DREQ8(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ9_READ	0x00000048 << 6	// LEVEL DREQ9(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ9_WRITE	0x0000004C << 6	// LEVEL DREQ9(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ10_READ	0x00000050 << 6	// LEVEL DREQ10(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ10_WRITE	0x00000054 << 6	// LEVEL DREQ10(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ11_READ	0x00000058 << 6	// LEVEL DREQ11(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ11_WRITE	0x0000005C << 6	// LEVEL DREQ11(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ12_READ	0x00000060 << 6	// LEVEL DREQ12(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ12_WRITE	0x00000064 << 6	// LEVEL DREQ12(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ13_READ	0x00000068 << 6	// LEVEL DREQ13(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ13_WRITE	0x0000006C << 6	// LEVEL DREQ13(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ14_READ	0x00000070 << 6	// LEVEL DREQ14(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ14_WRITE	0x00000074 << 6	// LEVEL DREQ14(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ15_READ	0x00000078 << 6	// LEVEL DREQ15(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ15_WRITE	0x0000007C << 6	// LEVEL DREQ15(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ16_READ	0x00000080 << 6	// LEVEL DREQ16(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ16_WRITE	0x00000084 << 6	// LEVEL DREQ16(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ17_READ	0x00000088 << 6	// LEVEL DREQ17(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ17_WRITE	0x0000008C << 6	// LEVEL DREQ17(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ18_READ	0x00000090 << 6	// LEVEL DREQ18(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ18_WRITE	0x00000094 << 6	// LEVEL DREQ18(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ19_READ	0x00000098 << 6	// LEVEL DREQ19(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ19_WRITE	0x0000009C << 6	// LEVEL DREQ19(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ20_READ	0x000000A0 << 6	// LEVEL DREQ20(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ20_WRITE	0x000000A4 << 6	// LEVEL DREQ20(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ21_READ	0x000000A8 << 6	// LEVEL DREQ21(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ21_WRITE	0x000000AC << 6	// LEVEL DREQ21(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ22_READ	0x000000B0 << 6	// LEVEL DREQ22(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ22_WRITE	0x000000B4 << 6	// LEVEL DREQ22(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ23_READ	0x000000B8 << 6	// LEVEL DREQ23(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ23_WRITE	0x000000BC << 6	// LEVEL DREQ23(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ24_READ	0x000000C0 << 6	// LEVEL DREQ24(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ24_WRITE	0x000000C4 << 6	// LEVEL DREQ24(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ25_READ	0x000000C8 << 6	// LEVEL DREQ25(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ25_WRITE	0x000000CC << 6	// LEVEL DREQ25(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ26_READ	0x000000D0 << 6	// LEVEL DREQ26(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DREQ26_WRITE	0x000000D4 << 6	// LEVEL DREQ26(Write)

#define	VCRSYS_DCBR_CIT_LEVEL_DACK0_READ	0x00000200 << 6	// LEVEL DACK0(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK0_WRITE	0x00000204 << 6	// LEVEL DACK0(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK1_READ	0x00000208 << 6	// LEVEL DACK1(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK1_WRITE	0x0000020C << 6	// LEVEL DACK1(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK2_READ	0x00000210 << 6	// LEVEL DACK2(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK2_WRITE	0x00000214 << 6	// LEVEL DACK2(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK3_READ	0x00000218 << 6	// LEVEL DACK3(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK3_WRITE	0x0000021C << 6	// LEVEL DACK3(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK4_READ	0x00000220 << 6	// LEVEL DACK4(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK4_WRITE	0x00000224 << 6	// LEVEL DACK4(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK5_READ	0x00000228 << 6	// LEVEL DACK5(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK5_WRITE	0x0000022C << 6	// LEVEL DACK5(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK6_READ	0x00000230 << 6	// LEVEL DACK6(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK6_WRITE	0x00000234 << 6	// LEVEL DACK6(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK7_READ	0x00000238 << 6	// LEVEL DACK7(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK7_WRITE	0x0000023C << 6	// LEVEL DACK7(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK8_READ	0x00000240 << 6	// LEVEL DACK8(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK8_WRITE	0x00000244 << 6	// LEVEL DACK8(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK9_READ	0x00000248 << 6	// LEVEL DACK9(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK9_WRITE	0x0000024C << 6	// LEVEL DACK9(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK10_READ	0x00000250 << 6	// LEVEL DACK10(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK10_WRITE	0x00000254 << 6	// LEVEL DACK10(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK11_READ	0x00000258 << 6	// LEVEL DACK11(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK11_WRITE	0x0000025C << 6	// LEVEL DACK11(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK12_READ	0x00000260 << 6	// LEVEL DACK12(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK12_WRITE	0x00000264 << 6	// LEVEL DACK12(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK13_READ	0x00000268 << 6	// LEVEL DACK13(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK13_WRITE	0x0000026C << 6	// LEVEL DACK13(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK14_READ	0x00000270 << 6	// LEVEL DACK14(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK14_WRITE	0x00000274 << 6	// LEVEL DACK14(Write)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK15_READ	0x00000278 << 6	// LEVEL DACK15(Read)
#define	VCRSYS_DCBR_CIT_LEVEL_DACK15_WRITE	0x0000027C << 6	// LEVEL DACK15(Write)