📄 startup.src
字号:
nop
mov.l #h'08000000, R0 ;DDR region
mov.b @R0, R1 ;Dummy Byte Read
mov.l #EMI_SCR_LOW, R0 ;MCU_SCR_L
mov.l #EMI_SCR_PALL, R1 ;PALL
mov.l R1, @R0
; nop
mov.l #EMI_SCR_CBR, R1 ;CBR
mov.l R1, @R0
; end of 2nd cut additional description for DDR
;*** about AutoRefresh for DDR-SDRAM
MOV.L #EMI_MIM_LOW,r0 ;MIM Register
MOV.L #EMI_MIM_SETUP2,r1 ;count Enable
MOV.L r1,@r0
nop
nop
; Change DDR PAD timing condition
MOV.L #LRAM_SP,r15 ;Stack Pointer is LRAM
.aif SH7770_REVISION eq SH7770_1STCUT
mov.l #_set_ddrpad,r0 ; Call ddrpad
.aelse
mov.l #_new_ddrpad_auto_head,r0 ; Call new ddrpad
.aendi
mov.l #ROMOFFSET, r1 ; need's wince
and r1, r0 ; need's wince
jsr @r0
nop
nop
; Check Watchdog timer status
.aif SH7770_REVISION ne SH7770_1STCUT
MOV.L #EXPEVT_REG, R0 ;EXPEVT
MOV.L #H'00000020, R1 ;Manual reset event code
MOV.L @R0, R2 ;
CMP/EQ R2,R1 ;Is EVT code 0x00000020(Manual reset)?
BT FlashToRam ;if R0=R1 then goto FlashToRam
mov.l #h'46, r2 ; 'F'
mov.l #LED_ALPHA, r3
mov.b r2, @r3
mov.l #h'41, r2 ; 'A'
add #LED_ALPHA_STRIDE, r3
mov.b r2, @r3
mov.l #h'49, r2 ; 'I'
add #LED_ALPHA_STRIDE, r3
mov.b r2, @r3
mov.l #h'4C, r2 ; 'L'
add #LED_ALPHA_STRIDE, r3
mov.b r2, @r3
mov.l #h'20, r2 ; ' '
add #LED_ALPHA_STRIDE, r3
mov.b r2, @r3
mov.l #h'57, r2 ; 'W'
add #LED_ALPHA_STRIDE, r3
mov.b r2, @r3
mov.l #h'44, r2 ; 'D'
add #LED_ALPHA_STRIDE, r3
mov.b r2, @r3
mov.l #h'54, r2 ; 'T'
add #LED_ALPHA_STRIDE, r3
mov.b r2, @r3
NOP
BRA $ ;while(1);
NOP
.aendi
FlashToRam:
; The bootloader is linked to run from RAM but is initially installed in FLASH
; at the SH-4's boot address. Now that memory has been configured, copy the
; entire bootloader image to RAM.
;
; N.B. The bootloader's region size must agree with eboot.bib's declaration of
; it.
mov.l #h'0002f000/4,r0 ; Size of bootloader's region in words
mov.l #h'a0000000,r1 ; Cached alias of loader's FLASH addr
mov.l #h'a8100000,r2 ; Cached alias of loader's RAM address
CopyLoop:
mov.l @r1,r3 ; Load next bootloader word
add #-1,r0 ; 1 less word to copy
mov.l r3,@r2 ; Store next bootloader word
cmp/eq #0,r0 ; Done?
add #4,r1 ; 4 more bytes loaded
bf/s CopyLoop ; (more of Done?)
add #4,r2 ; 4 more bytes stored
; Flush then enable the cache in copy-back mode.
mov.l #CCN_CCR,r1
mov.l #CCN_CCR_FLUSH,r0 ; Flush the cache
mov.l r0,@r1
mov #CCN_CCR_ENABLE,r0 ; Enable the cache
mov.l r0,@r1
nop
nop
nop
mov #Stack,r15 ; Set up a stack
; The bootloader is linked to run in section P1 (cached) but is started at
; reset in section P2 (uncached). Now that memory has been configured and the
; cache turned on, the jsr to _main (an absolute address) also branches from
; section P2 to section P1, effectively enabling the cache at the same time.
mov.l #_main,r0 ; Call main
jsr @r0 ; Should never return
nop
HaltLoop:
bra HaltLoop ; If return, stop with LEDs = 0x0f
nop
ENTRY_END _StartUp
;++
;
; void Launch(
; unsigned long pFunc
; )
;
; Routine Description:
;
; This function launches the program at pFunc. The expectation is that
; the launched program never returns.
;
; Arguments:
;
; pFunc (r4) - Supplies the address of the program to launch.
;
; Return Value:
;
; None; the launched program never returns.
;
;--
LEAF_ENTRY _Launch
jmp @r4
nop
ENTRY_END _Launch
LEAF_ENTRY _LaunchExisting
jmp @r4
nop
ENTRY_END _LaunchExisting
; DEBUGTIME .equ 0 ; Disable debug timing
DEBUGTIME .equ 1 ; Enable debug timing
.aif DEBUGTIME
LoopCount .equ 50000000
LEAF_ENTRY _Time1
mov #LoopCount,r0
T1Loop:
dt r0
bf T1Loop
rts
nop
ENTRY_END _Time1
LEAF_ENTRY _Time2
mov #LoopCount,r0
T2Loop:
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
dt r0
bf T2Loop
rts
nop
ENTRY_END _Time2
LEAF_ENTRY _Time3
mov #LoopCount,r0
T3Loop:
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
dt r0
bf T3Loop
rts
nop
ENTRY_END _Time3
.aendi
.aif SH7770_REVISION eq SH7770_1STCUT
;---------------------------------------------------------------------------
;
; Change DDR PAD timing condition by S.Matsui (CODE)
;
; .align 4
; .export _set_ddrpad
LEAF_ENTRY _set_ddrpad
MOV.L R0,@-R15
MOV.L R1,@-R15
MOV.L R2,@-R15
MOV.L R3,@-R15
MOV.L R4,@-R15
STS.L PR,@-R15
;xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
MOV.L #H'FEA00004,R2
MOV.L #H'0000A55A,R0
MOV.L R0,@R2
;
MOV.L #H'FEA0000C,R2
MOV.L #H'01010000,R0
MOV.L R0,@R2
;
MOV.L #H'FEB00014,R2
MOV.L #H'00080000,R0
MOV.L R0,@R2
;
MOV.L #H'FEB00004,R2
MOV.L #H'00010000,R0
MOV.L R0,@R2
;
MOV.L #ddrpad_data,R3
mov.l #ROMOFFSET, r2 ; need's wince
and r2, r3 ; need's wince
MOV.L #H'FEB00014,R2
MOV.L #H'00080000,R0
;
MOV #H'08,R4
;
_set_ddrpad_L1
MOV.B #H'E0,R1
AND R1,R0
MOV.B @R3+,R1
ADD R1,R0
MOV.L R0,@R2
MOV.L #H'00000800,R1
OR R1,R0
MOV.L R0,@R2
XOR R1,R0
MOV.L R0,@R2
;
MOV.L #H'00001100,R1
ADD R1,R0
;
ADD #-1,R4
CMP/PL R4
BT _set_ddrpad_L1
nop
;
MOV #H'08,R4
MOV.L #H'00080000,R0
;
_set_ddrpad_L2
MOV.B #H'E0,R1
AND R1,R0
MOV.B @R3+,R1
ADD R1,R0
MOV.L R0,@R2
MOV.L #H'00008000,R1
OR R1,R0
MOV.L R0,@R2
XOR R1,R0
MOV.L R0,@R2
;
MOV.L #H'00001100,R1
ADD R1,R0
;
ADD #-1,R4
CMP/PL R4
BT _set_ddrpad_L2
nop
LDS.L @R15+,PR
MOV.L @R15+,R4
MOV.L @R15+,R3
MOV.L @R15+,R2
MOV.L @R15+,R1
MOV.L @R15+,R0
RTS
nop
;
.align 4
ddrpad_data:
.DATA.L H'01010101
.DATA.L H'01010101
.DATA.L H'01010101
.DATA.L H'01010101
; .END
ENTRY_END _set_ddrpad
.aelse ;"SH7770_1STCUT"
;**********************************************************
;
; Copyright (C) Renesas Technology Corp. 2004. All Rights Reserved
;
; Optimum delay value search and set program
;
; FILE : new_ddr_auto_0.src
; CREATED : 2004.3.25
; AUTHOR : Renesas Technology Corp.
; HISTORY :
; 2004.3.25
; - Created release code
;
; ==================================================================================
; Caution !!!
; ==================================================================================
; (a) This program assumes that user uses R15 as a stack pointer.
; (b) Stack data should not be stored on DDR-SDRAM.
; (c) While this program is executed, other program must not use DDR-SDRAM.
; (d) If this program stored on cache, the execution time will be reduced.
;
; ==================================================================================
; Used data area
; ==================================================================================
; DDR_WORK : H'AFE6A000
; DDR_UPPER : H'AFE6A400
; Used range [ H'AFE6A000 - H'AFE6A3FF ] : 1024 Bytes
; ( Data used for reading data )
; ---------------------------------------------------------------------------------
; LRAM_REF : H'E500E000
; Used range [ H'E500E000 - H'E500E3FF ] : 1024 Bytes
; ( Used for comparing with the data read from DDR-SDRAM )
; ---------------------------------------------------------------------------------
; LRAM_WORK : H'E500F000
; Used range [ H'E500F000 - H'E500F01F ] : 32 Bytes
; ( Temporarily used for storing data from DDR-SDRAM )
; ---------------------------------------------------------------------------------
; LRAM_RESULT : H'E500F030
; Used range [ H'E500F024 - H'E500F02F ] : 12 Bytes
; ( Used for storing register setting values )
; ---------------------------------------------------------------------------------
; LRAM_STOCK : H'E500F100
; Used range [ H'E500F0D8 - H'E500F0FF ] : 40 Bytes
; ( 10 times measurement results are stored )
;
; ==================================================================================
; Behavior explanation
; ==================================================================================
; This program is designed to search and set an optimum delay value for
; the modules of DQS 90 degree phase shift.
;
; The program procedure is done as follows.
; (1) Transfer the stored data in this program to LRAM area.
; The data on LRAM area are used to compare with the data read from DDR-SDRAM.
; (2) Read the data on LRAM area, and write those to DDR-SDRAM area.
; (3) The delay value for the modules of DQS 90 degree phase shift is set to zero.
; (4) Read the data on DDR-SDRAM area, and compare those with the data on LRAM area.
; Store a result (pass/fail) to a bit of the general register (R6).
; (5) Add 1 to the delay value. Repeat (4) until the delay value becomes 32.
; (6) Store results (R6) to LRAM area. Repeat (3)(4)(5) 9 times.
; (In totality, the measurement is done 10 times.)
; (7) Apply OR-operations to the stored 10 results,
; and store the calculated result to the general register (R0).
; (8) Search in R0 minimum[min] and maximum[max] values
; with which data can be successfully read from DDR-SDRAM.
; (9) Calculate [ MAX{ ( min + max + 2 ) / 4 , min } ],
; and set that value as the optimum delay value.
;
; See application note for more details.
;=====================================================
; .section ddrpad_1, code, align=4
; .align 4
; .export _new_ddrpad_auto_head
LEAF_ENTRY _new_ddrpad_auto_head
;=====================================================
CHECK_UPPER .EQU H'400 ;FINAL DATA address offset
RETRY_UPPER .EQU H'A ;DDR-RD RETRY Count
LRAM2DDR .EQU H'20 ;32byte data transfer 32 times
CODE_MAX .EQU H'20 ;Delay0~31 Count
LRAM_REF .EQU H'E500E000 ;CS0->LRAM(000->3FF,1024Byte)
LRAM_WORK .EQU H'E500F000 ;DDR -> LRAM(00->1F,32Byte)
LRAM_RESULT .EQU H'E500F030 ;REG MONITOR(24->2F,12Byte)
LRAM_STOCK .EQU H'E500F100 ;CODE data(0D8->0FF,40Byte)
DDR_WORK .EQU H'AFE6A000 ;DDR work area top
DDR_UPPER .EQU H'AFE6A400 ;1024Byte final address
SHDMAC0_SET .EQU H'00105401 ;32byte SRCinc DESinc AutoReq
SHDMAC_SET .EQU H'00100421 ;32byte Burst AutoReq
SHDMASAR0 .EQU H'FE008020 ;DMA source address
SHDMADAR0 .EQU H'FE008024 ;DMA destination address
SHDMATCR0 .EQU H'FE008028 ;DMA transfer count
SHDMACHCR0 .EQU H'FE00802C ;DMA channel control
SHDMACOR .EQU H'FE008060 ;DMA operation
SHDMAC_OR_DME .EQU H'00000001
SHDMAC_CHCR_TE .EQU H'00000002
;=====================================================
.ALIGN 4
;_new_ddrpad_auto_head
;xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
; main prog start xxxxxxxxxxxx
;xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
MOV.L R0, @-R15
MOV.L R1, @-R15
MOV.L R2, @-R15
MOV.L R3, @-R15
MOV.L R4, @-R15
MOV.L R5, @-R15
MOV.L R6, @-R15
MOV.L R7, @-R15
MOV.L R8, @-R15
MOV.L R9, @-R15
MOV.L R10, @-R15
MOV.L R11, @-R15
MOV.L R12, @-R15
MOV.L R13, @-R15
MOV.L R14, @-R15
STS.L PR, @-R15
MOV.L #DATA_AREA, R0 ; DATA_AREA->LRAM
mov.l #ROMOFFSET, r2 ; need's wince
and r2, r0 ; need's wince
MOV.L #CHECK_UPPER, R1 ; DATA number
SHLR2 R1 ;
MOV.L #LRAM_REF, R2 ; Reference top address
_REF_COPY
MOV.L @R0+, R3
MOV.L R3, @R2
ADD.L #h'4, R2
DT R1
BF _REF_COPY
NOP
MOV.L #H'FEA00004, R0
MOV.L #H'0000A55A, R1
MOV.L R1, @R0 ;LOCK OFF
;xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
;xxxxx DQS START xxx
;xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
CASE_DQS0
;DPCTL0[16]=1 , [1]=1
MOV.L #H'FEA0000C, R0 ;
MOV.L #H'00010002, R1
MOV.L R1, @R0 ;dqsattrkoff=1,heat_up=off
;DDRBIST1[16]=1
MOV.L #H'FEB00004, R0 ;
MOV.L #H'00010000, R1
MOV.L R1, @R0 ;DQSOEN=1
MOV.L #H'FE800014, R0 ;refresh
MOV.L #H'00000002, R1
MOV.L R1, @R0 ;SCR(-PALL-)
MOV.L #H'00000004, R1
MOV.L R1, @R0 ;SCR(-REF-)
;************************************************
; autoDMA 32byte cs0=>cs2(DDR)
;
; Reference ON LRAM -> DDR
;************************************************
MOV.L #SHDMASAR0, R0 ; Source set
MOV.L #LRAM_REF, R1 ; Reference address
MOV.L R1, @R0 ;
MOV.L #SHDMADAR0, R0 ; Destination
MOV.L #DDR_WORK, R1 ; DDR WORK area top
MOV.L R1, @R0 ;
MOV.L #SHDMATCR0, R0 ; Transfer count
MOV.L #LRAM2DDR, R1 ;
MOV.L R1, @R0 ;
MOV.L #SHDMACHCR0, R0
MOV.L #SHDMAC0_SET, R1 ; 32byte SRC:inc DES:inc AutoReq
MOV.L R1, @R0 ; cycle steal
MOV.L #SHDMACOR, R2
MOV.W #SHDMAC_OR_DME,R1 ;; start
MOV.W R1, @R2
MOV.L #SHDMAC_CHCR_TE, R1 ; Finish ?
LRAM2DDR_WAIT
MOV.L @R0, R3
TST R1, R3
BT LRAM2DDR_WAIT
NOP
;************************************************
; LRAM STOCK area initialization
;
;************************************************
MOV.L #LRAM_STOCK, R0
MOV.L #RETRY_UPPER, R1
MOV.L #H'00000000, R2
STOCK_CLEAR
MOV.L R2, @-R0
DT R1
BF STOCK_CLEAR
NOP
;************************************************
; Compare initialization
;
; R0 : Repeat counter (code0->1F)
; R1 : Retry counter (10 time)
; R2 : Free
; R3 : DQSLVSET pad selector data
; R4 : DQSLVSET pad shift data
; R5 : DQSLVSET address
; R6 : PASS/FAIL flag
; R7 : Addisional data
; R8 : Loop counter
; R14: PASS/FAIL flag data stock address
;************************************************
MOV.L #RETRY_UPPER, R1 ;retry counter
MOV.L #LRAM_STOCK, R14
;----
;repeat of case0~31, dqsat_c[4:0]=00000~11111, Deley=0~31buf
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