drv_glob.h

WinCE5.0BSP for Renesas SH7770

//
//  Copyright(C) Renesas Technology Corp. 1998-2005. All rights reserved.
//
//  header file for ITS-DS7 Ver.1.0.0
//
//  FILE      : drv_glob.h
//  CREATED   : 2002.04.25
//  MODIFIED  : 2005.06.09
//  AUTHOR    : Renesas Technology Corp.
//  HARDWARE  : RENESAS ITS-DS7
//  HISTORY   : 
//              2003.06.20
//              - Created release code.
//                (based on RENESAS ITS-DS4 Source Kit Ver.1.2.0 for WCE4.2)
//              2003.12.18
//              - change driver buffer allocation.
//              2004.02.06
//              - change scif buffer size.
//              2005.05.10
//              - Supported Passive KITL.
//              2005.06.09
//              - Modified memory mapping for Multiple XIP.
//

#ifndef _DRV_GLOB_H
#define _DRV_GLOB_H

#include <halether.h>  // Ethernet debug defs
#pragma pack(1)

#define PAD(label,amt)  UCHAR Pad##label[amt]

// Make sure these match up with the defs in config.bib, and drv_glob.inc
#define DRIVER_GLOBALS_PHYSICAL_MEMORY_START  DRV_GLOBAL_BASE
#define DRIVER_GLOBALS_PHYSICAL_MEMORY_SIZE   0x1000  // 4K

// Audio globals.  

typedef struct _AUDIO_GLOBALS 
{
	// Used to let HAL know which level ints are enabled.
	DWORD  play_address;   
	USHORT outInt;
	USHORT dammy1;
	DWORD  play_pointer;		//for TMU2
	DWORD  rec_address;
	USHORT inInt;
	USHORT dammy2;
	int	PLAY_CH;	// DMA Transfer Ch for Playback
	int	REC_CH;		// DMA Transfer Ch for Recording
	int	HW_VOLUME;	// H/W Volume Control(1:H/W 0:S/W)
	PAD(0,224);          // Pad to 256 bytes
    
} AUDIO_GLOBALS, *PAUDIO_GLOBALS;
#define	PLAY_ADDRESS_OFFSET	0
#define	OUTINT_OFFSET		4
#define	PLAY_POINTER_OFFSET	8
#define	REC_ADDRESS_OFFSET	12
#define	ININT_OFFSET		16
#define	PLAY_CH_OFFSET		20
#define	REC_CH_OFFSET		24
#define	HW_VOLUME_OFFSET	28

// PCMCIA globals.  
typedef struct _PCMCIA_GLOBALS 
{
	// Used to let HAL know which level ints are enabled.
	USHORT slot0Enable;   
	USHORT slot1Enable;
	PAD(0,252);          // Pad to 256 bytes
    
} PCMCIA_GLOBALS, *PPCMCIA_GLOBALS;

// DISPLAY globals. 
typedef struct _DISPLAY_GLOBALS 
{
	PAD(0,256);                     // Reserved. Pad to 256 bytes
    
} DISPLAY_GLOBALS, *PDISPLAY_GLOBALS;

// For debugging over ethernet. Controls debug messages, ethernet shell
// and kernel debugger.  Note that this struct should not be zeroed
// out by OEMInit, as the eboot bootloader passes us state info.
#define EBOOT_MAGIC_NUM 0x45424F54	// "EBOOT"
typedef struct _DBG_ETH_GLOBALS 
{
	DWORD EbootMagicNum;			// To detect if ether bootloader is present
	UCHAR etherEnabled;				// If non-zero, ethernet card present
	UCHAR etherFlags;				// Set by eboot loader. Controls which components are enabled over ether (see ethdbg.h)
	UCHAR etherAdapter;				// type of adapter used in system.  If the bootloader uses a specific adapter, the HAL must also
	UCHAR pad;

	EDBG_ADDR PlatformAddr;			// IP and ether address of S1
	DWORD SubnetMask;				// Subnet mask

	EDBG_ADDR DownloadHostAddr;		// IP and ether address of host who started us

	// The following addresses are assumed valid if the corresponding flag in
	// etherFlags is set.
	EDBG_ADDR DbgHostAddr;			// IP/ether addr and UDP port of host receiving dbg msgs
	EDBG_ADDR KdbgHostAddr;			// IP/ether addr and UDP port of host running kernel debugger
	EDBG_ADDR PpshHostAddr;			// IP/ether addr and UDP port of host running ether text shell
    DWORD DHCPLeaseTime;			// DHCP lease duration in seconds.
    DWORD EdbgFlags;				// Information about ethernet system

    WORD KitlTransport;         // Transport for Kitl communication    
	PAD(1,2);

	UCHAR fmtBuf[172];				// Tx Buffer for debug messages (ASCII)
} DBG_ETH_GLOBALS, *PDBG_ETH_GLOBALS;

#define DBG_ETH_GLOBALS_SIZE 256

extern BOOL DebugEtherPresent;

#define ETH_NONE      0
#define ETH_SMC9000   1
//#define ETH_NE2000PC  2

typedef struct _DRIVER_GLOBALS
{
	AUDIO_GLOBALS	aud[4];			// Offset 0x000
	PCMCIA_GLOBALS	pcm;			// Offset 0x100
	DISPLAY_GLOBALS disp;           // Offset 0x200
	int		aud_index_hac;
	int		aud_index_hssi1;
	int		aud_index_hssi2;
	int		aud_index_src;
	char	dma_interrupt[32];
#if (SH7770_REVISION == SH7770_1STCUT)
	int		TSTR0;
	int		TSTR1;
	int		TSTR2;
	int		TSTR_DMY;
	PAD(0, 0x1B8);
#else
	PAD(0, 0x1C8);
#endif
	DWORD dwLastLaunchAddrValid;
	DWORD dwLastLaunchAddr;
	// The following structs will not be zero initialized (see defs above)
	DBG_ETH_GLOBALS eth;			// Offset 0x800
} DRIVER_GLOBALS, *PDRIVER_GLOBALS;

#define	PCMCIA_GLOBALS_OFFSET		0x0400
#define	DISPLAY_GLOBALS_OFFSET		0x0500
#define	AUD_INDEX_HAC_OFFSET		0x0600
#define	AUD_INDEX_HSSI1_OFFSET		0x0604
#define	AUD_INDEX_HSSI2_OFFSET		0x0608
#define	AUD_INDEX_SRC_OFFSET		0x060c
#define	DMA_INTERRUPT_FLG_OFFSET	0x0610
#if (SH7770_REVISION == SH7770_1STCUT)
#define	TSTR0_GLOBAL_OFFSET		0x0630
#define	TSTR1_GLOBAL_OFFSET		0x0634
#define	TSTR2_GLOBAL_OFFSET		0x0638
#endif

// ATAPI globals.  
#define ATAPI_GLOBALS_OFFSET		0x0900	// DRIVER GLOBALS start address + 0x0900
#define G_ATAPI_FLAG_BASE			(DRV_GLOBAL_BASE + ATAPI_GLOBALS_OFFSET)	// ATAPI MASTER/SLAVE Flags Register	
#define G_ATAPI_FLAG_SIZE			0x10  


// EDBG definitions
//#define EDBG_PHYSICAL_MEMORY_START	(DRV_GLOBAL_BASE + 0x00030000)
#define EDBG_PHYSICAL_MEMORY_START	(DRV_GLOBAL_BASE + 0x00001000)

#define DRV_BUF_OFFSET				0x00021000

// ATAPI buffer
#define ATAPI_BUFFER_OFFSET			(DRV_BUF_OFFSET + 0x00000000)
#define ATAPI_BUFFER_BASE			(DRV_GLOBAL_BASE + ATAPI_BUFFER_OFFSET)
#define ATAPI_BUFFER_SIZE			0x00020000

// SPDIF buffer
#define SPDIF_BUFFER_OFFSET			(DRV_BUF_OFFSET + 0x00020000)
#define SPDIF_BUFFER_BASE			(DRV_GLOBAL_BASE + SPDIF_BUFFER_OFFSET)
#define SPDIF_BUFFER_SIZE			0x00060000
#define SPDIF_BUFFER_BASE2			(SPDIF_BUFFER_BASE+0x00020000)
#define SPDIF_BUFFER_SIZE2			0x00040000

// AUDIO buffer
#define AUDIO_DMA_PAGE_SIZE			0x00002000
// for Playback
#define AUDIO_P_BUFFER_OFFSET		(DRV_BUF_OFFSET + 0x00080000)
#define AUDIO_P_BUFFER_BASE			(DRV_GLOBAL_BASE + AUDIO_P_BUFFER_OFFSET)
#define AUDIO_P_BUFFER_SIZE			0x00008000	// 2Page * 2ch
// for Record
#define AUDIO_R_BUFFER_OFFSET		(DRV_BUF_OFFSET + 0x00088000)
#define AUDIO_R_BUFFER_BASE			(DRV_GLOBAL_BASE + AUDIO_R_BUFFER_OFFSET)
#define AUDIO_R_BUFFER_SIZE			0x00008000	// 2Page * 2ch

// USB buffer
#define USB_BUFFER_OFFSET			(DRV_BUF_OFFSET + 0x00096000)
#define USB_BUFFER_BASE				(DRV_GLOBAL_BASE + USB_BUFFER_OFFSET)
#define USB_BUFFER_SIZE				0x0001a000

// I2C buffer
#define I2C_BUFFER_OFFSET			(DRV_BUF_OFFSET + 0x00090000)
#define I2C_BUFFER_BASE				(DRV_GLOBAL_BASE + I2C_BUFFER_OFFSET)
#define I2C_BUFFER_SIZE				0x00001000

// SCIF0 buffer
#define SCIF0_BUFFER_OFFSET			(DRV_BUF_OFFSET + 0x00091000)
#define SCIF0_TXBUFFER_SIZE			0x00000400
#define SCIF0_RXBUFFER_SIZE			0x00000080
#define SCIF0_TX_BUFFER_BASE			(DRV_GLOBAL_BASE + SCIF0_BUFFER_OFFSET)
#define SCIF0_RX_BUFFER_BASE			(SCIF0_TX_BUFFER_BASE+0x1000)

// SPDIF buffer
#define SPDIF_GLOBAL_OFFSET			(DRV_BUF_OFFSET + 0x00093000)
#define SPDIF_GLOBAL_BASE			(DRV_GLOBAL_BASE + SPDIF_GLOBAL_OFFSET)
#define SPDIF_GLOBAL_SIZE			0x00001000

// SCIF3 buffer
#define SCIF3_BUFFER_OFFSET			(DRV_BUF_OFFSET + 0x00094000)

#define SCIF3_TXBUFFER_SIZE			0x00000400
#define SCIF3_RXBUFFER_SIZE			0x00000080

#define SCIF3_TX_BUFFER_BASE			(DRV_GLOBAL_BASE + SCIF3_BUFFER_OFFSET)
#define SCIF3_RX_BUFFER_BASE			(DRV_GLOBAL_BASE + SCIF3_BUFFER_OFFSET + 0x1000)

// Add pointer to off button flag
#pragma pack()

// Prototype functions from drvlib
#ifdef __cplusplus
extern "C" {
#endif
void DriverSleep(DWORD dwMS, BOOL bInPowerHandler);
#ifdef __cplusplus
}
#endif

#endif // _DRV_GLOB_H