realtekr1000.cpp

Mac OS X 下的网卡驱动

}

bool RealtekR1000::R1000ProbeAndStartBoard()
{
	if (!R1000InitBoard()) return false;

	curr_mtu_size = DEFAULT_MTU;
	tx_pkt_len = DEFAULT_MTU + ETH_HDR_LEN;
	rx_pkt_len = DEFAULT_MTU + ETH_HDR_LEN;
	hw_rx_pkt_len = rx_pkt_len + 8;
	
	//Config PHY
	R1000HwPhyConfig();
	
	DLog("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
	WriteMMIO8(0x82, 0x01);
	if (mcfg < MCFG_METHOD_3)
	{
		DLog("Set PCI Latency=0x40\n");
		pciDev->configWrite8(kIOPCIConfigLatencyTimer, 0x40);
	}
	
	if (mcfg == MCFG_METHOD_2)
	{
		DLog("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
		WriteMMIO8(0x82, 0x01);
		DLog("Set PHY Reg 0x0bh = 0x00h\n");
		WriteGMII32(0x0b, 0x0000);	//w 0x0b 15 0 0
	}
	
	int speed_opt = SPEED_100;
	int duplex_opt = DUPLEX_FULL;
	int autoneg_opt = AUTONEG_ENABLE;
	int val = 0;
		
	// if TBI is not endbled
	if (!(ReadMMIO8(PHYstatus) & TBI_Enable))
	{
		val = ReadGMII32(PHY_AUTO_NEGO_REG);
		val |= PHY_Cap_PAUSE | PHY_Cap_ASYM_PAUSE ;

		R1000SetMedium(speed_opt, duplex_opt, autoneg_opt);
	}// end of TBI is not enabled
	else
	{
		IODelay(100);
		DLog("1000Mbps Full-duplex operation, TBI Link %s!\n", (ReadMMIO32(TBICSR) & TBILinkOK) ? "OK" : "Failed" );
	}// end of TBI is not enabled
	
#ifdef DEBUG	
	if (ReadMMIO8(PHYstatus) & LinkStatus)
	{
		DLog("Link Status: %s\n","Linked");

		if (ReadMMIO8(PHYstatus) & _1000Mbps) DLog("Link Speed: 1000Mbps\n");
		else if(ReadMMIO8(PHYstatus) & _100Mbps) DLog("Link Speed: 100Mbps\n");
		else if(ReadMMIO8(PHYstatus) & _10Mbps) DLog("Link Speed: 10Mbps\n");

		DLog("Duplex mode: %s\n", ReadMMIO8(PHYstatus) & FullDup ? "Full-Duplex" : "Half-Duplex");
	}
	else
	{
		DLog("Link Status: %s\n","Not Linked");
	}
#endif

	return true;
}
	
bool RealtekR1000::R1000StopBoard()
{
	return true;
}

bool RealtekR1000::R1000SetSpeedDuplex(ulong anar, ulong gbcr, ulong bmcr)
 {
	unsigned int i = 0;
	unsigned int bmsr;

	WriteGMII32(PHY_AUTO_NEGO_REG, anar);
	WriteGMII32(PHY_1000_CTRL_REG, gbcr);
	WriteGMII32(PHY_CTRL_REG, bmcr);

	for(i=0; i<10000; i++)
	{
		bmsr = ReadGMII32(PHY_STAT_REG);
		if (bmsr & PHY_Auto_Neco_Comp) return true;
	}
	return false;	
}


bool RealtekR1000::R1000SetMedium(ushort speed, uchar duplex, uchar autoneg)
{
	ulong anar=0, gbcr=0, bmcr=0, val=0;

	val = ReadGMII32(PHY_AUTO_NEGO_REG);
	val |= PHY_Cap_PAUSE | PHY_Cap_ASYM_PAUSE ;

	bmcr = PHY_Restart_Auto_Nego|PHY_Enable_Auto_Nego;

	if(autoneg == AUTONEG_ENABLE)
	{
		this->autoneg = AUTONEG_ENABLE;
		anar = PHY_Cap_10_Half | PHY_Cap_10_Full | PHY_Cap_100_Half | PHY_Cap_100_Full;
		gbcr = PHY_Cap_1000_Half | PHY_Cap_1000_Full;
	}
	else
	{
		this->autoneg = AUTONEG_DISABLE;
		if(speed == SPEED_1000)
		{
			this->speed = SPEED_1000;
			this->duplex = DUPLEX_FULL;

			anar = PHY_Cap_10_Half | PHY_Cap_10_Full | PHY_Cap_100_Half | PHY_Cap_100_Full;
			if ((mcfg == MCFG_METHOD_13) || (mcfg == MCFG_METHOD_14) ||
				 (mcfg == MCFG_METHOD_15)) gbcr = PHY_Cap_Null;
			else gbcr = PHY_Cap_1000_Half | PHY_Cap_1000_Full;
		}
		else if ((speed == SPEED_100) && (duplex == DUPLEX_FULL))
		{
			this->speed = SPEED_100;
			this->duplex = DUPLEX_FULL;

			anar = PHY_Cap_10_Half | PHY_Cap_10_Full | PHY_Cap_100_Half | PHY_Cap_100_Full;
			gbcr = PHY_Cap_Null;
		}
		else if (( speed == SPEED_100) && (duplex == DUPLEX_HALF))
		{
			this->speed = SPEED_100;
			this->duplex = DUPLEX_HALF;

			anar = PHY_Cap_10_Half | PHY_Cap_10_Full | PHY_Cap_100_Half;
			gbcr = PHY_Cap_Null;
		}
		else if((speed == SPEED_10) && (duplex == DUPLEX_FULL))
		{
			this->speed = SPEED_10;
			this->duplex = DUPLEX_FULL;

			anar = PHY_Cap_10_Half | PHY_Cap_10_Full;
			gbcr = PHY_Cap_Null;
		}
		else if ((speed == SPEED_10) && (duplex == DUPLEX_HALF))
		{
			this->speed = SPEED_10;
			this->duplex = DUPLEX_HALF;

			anar = PHY_Cap_10_Half;
			gbcr = PHY_Cap_Null;
		}
		else
		{
			this->speed = SPEED_100;
			this->duplex = DUPLEX_FULL;

			anar = PHY_Cap_10_Half|PHY_Cap_10_Full|PHY_Cap_100_Half|PHY_Cap_100_Full;
			gbcr = PHY_Cap_Null;
		}
	}

	//enable flow control
	anar |=  val & 0xC1F;

	return R1000SetSpeedDuplex(anar, gbcr, bmcr);
}


void RealtekR1000::R1000HwPhyReset()
{
	int val, phy_reset_expiretime = 50;

	DLog("Reset PHY\n");
	val = (ReadGMII32(0) | 0x8000) & 0xffff;
	WriteGMII32(0, val);

	do //waiting for phy reset
	{
		if (ReadGMII32(0) & 0x8000)
		{
			phy_reset_expiretime --;
			IODelay(100);
		}
		else
		{
			break;
		}
	}
	while (phy_reset_expiretime >= 0);
}

void RealtekR1000::R1000HwPhyConfig()
{
	DLog("PHY config\n");

	if (mcfg == MCFG_METHOD_4 )
	{
#if 0
		WriteGMII32(0x1F, 0x0001);
		WriteGMII32(0x1b, 0x841e);
		WriteGMII32(0x0e, 0x7bfb);
		WriteGMII32(0x09, 0x273a);
#endif
		WriteGMII32(0x1F, 0x0002);
		WriteGMII32(0x01, 0x90D0);
		WriteGMII32(0x1F, 0x0000);
	}
	else if ((mcfg == MCFG_METHOD_2) || (mcfg == MCFG_METHOD_3))
	{
		WriteGMII32(0x1f, 0x0001);
		WriteGMII32(0x06, 0x006e);
		WriteGMII32(0x08, 0x0708);
		WriteGMII32(0x15, 0x4000);
		WriteGMII32(0x18, 0x65c7);

		WriteGMII32(0x1f, 0x0001);
		WriteGMII32(0x03, 0x00a1);
		WriteGMII32(0x02, 0x0008);
		WriteGMII32(0x01, 0x0120);
		WriteGMII32(0x00, 0x1000);
		WriteGMII32(0x04, 0x0800);
		WriteGMII32(0x04, 0x0000);

		WriteGMII32(0x03, 0xff41);
		WriteGMII32(0x02, 0xdf60);
		WriteGMII32(0x01, 0x0140);
		WriteGMII32(0x00, 0x0077);
		WriteGMII32(0x04, 0x7800);
		WriteGMII32(0x04, 0x7000);

		WriteGMII32(0x03, 0x802f);
		WriteGMII32(0x02, 0x4f02);
		WriteGMII32(0x01, 0x0409);
		WriteGMII32(0x00, 0xf0f9);
		WriteGMII32(0x04, 0x9800);
		WriteGMII32(0x04, 0x9000);

		WriteGMII32(0x03, 0xdf01);
		WriteGMII32(0x02, 0xdf20);
		WriteGMII32(0x01, 0xff95);
		WriteGMII32(0x00, 0xba00);
		WriteGMII32(0x04, 0xa800);
		WriteGMII32(0x04, 0xa000);

		WriteGMII32(0x03, 0xff41);
		WriteGMII32(0x02, 0xdf20);
		WriteGMII32(0x01, 0x0140);
		WriteGMII32(0x00, 0x00bb);
		WriteGMII32(0x04, 0xb800);
		WriteGMII32(0x04, 0xb000);

		WriteGMII32(0x03, 0xdf41);
		WriteGMII32(0x02, 0xdc60);
		WriteGMII32(0x01, 0x6340);
		WriteGMII32(0x00, 0x007d);
		WriteGMII32(0x04, 0xd800);
		WriteGMII32(0x04, 0xd000);

		WriteGMII32(0x03, 0xdf01);
		WriteGMII32(0x02, 0xdf20);
		WriteGMII32(0x01, 0x100a);
		WriteGMII32(0x00, 0xa0ff);
		WriteGMII32(0x04, 0xf800);
		WriteGMII32(0x04, 0xf000);

		WriteGMII32(0x1f, 0x0000);
		WriteGMII32(0x0b, 0x0000);
		WriteGMII32(0x00, 0x9200);
#if 0
		WriteGMII32(0x1F, 0x0001);
		WriteGMII32(0x15, 0x1000);
		WriteGMII32(0x18, 0x65C7);
		WriteGMII32(0x04, 0x0000);
		WriteGMII32(0x03, 0x00A1);
		WriteGMII32(0x02, 0x0008);
		WriteGMII32(0x01, 0x1020);
		WriteGMII32(0x00, 0x1000);
		WriteGMII32(0x04, 0x0800);
		WriteGMII32(0x04, 0x0000);
		WriteGMII32(0x04, 0x7000);
		WriteGMII32(0x03, 0xFF41);
		WriteGMII32(0x02, 0xDE60);
		WriteGMII32(0x01, 0x0140);
		WriteGMII32(0x00, 0x0077);
		WriteGMII32(0x04, 0x7800);
		WriteGMII32(0x04, 0x7000);
		WriteGMII32(0x04, 0xA000);
		WriteGMII32(0x03, 0xDF01);
		WriteGMII32(0x02, 0xDF20);
		WriteGMII32(0x01, 0xFF95);
		WriteGMII32(0x00, 0xFA00);
		WriteGMII32(0x04, 0xA800);
		WriteGMII32(0x04, 0xA000);
		WriteGMII32(0x04, 0xB000);
		WriteGMII32(0x03, 0xFF41);
		WriteGMII32(0x02, 0xDE20);
		WriteGMII32(0x01, 0x0140);
		WriteGMII32(0x00, 0x00BB);
		WriteGMII32(0x04, 0xB800);
		WriteGMII32(0x04, 0xB000);
		WriteGMII32(0x04, 0xF000);
		WriteGMII32(0x03, 0xDF01);
		WriteGMII32(0x02, 0xDF20);
		WriteGMII32(0x01, 0xFF95);
		WriteGMII32(0x00, 0xBF00);
		WriteGMII32(0x04, 0xF800);
		WriteGMII32(0x04, 0xF000);
		WriteGMII32(0x04, 0x0000);
		WriteGMII32(0x1F, 0x0000);
		WriteGMII32(0x0B, 0x0000);
#endif
	}
	
	DLog("tell card we can powersave");
	WriteMMIO8(Config1, ReadMMIO8(Config1) | PMEnable);
	WriteMMIO8(Config5, ReadMMIO8(Config5) & PMEStatus);
	
}

void RealtekR1000::R1000HwStart()
{
	u32 i;
	u8 i8;
	u16 i16;
	
	if ((mcfg != MCFG_METHOD_5) && (mcfg != MCFG_METHOD_11) &&
	   (mcfg != MCFG_METHOD_12) && (mcfg != MCFG_METHOD_13) &&
	   (mcfg != MCFG_METHOD_14) && (mcfg != MCFG_METHOD_15))
	{
		/* Soft reset the chip. */
		WriteMMIO8 ( ChipCmd, CmdReset);

		/* Check that the chip has finished the reset. */
		for (i = 1000; i > 0; i--)
		{
			if ((ReadMMIO8( ChipCmd ) & CmdReset) == 0) break;
			else IODelay(10);
		}
			
		WriteMMIO8(Cfg9346, Cfg9346_Unlock);
		WriteMMIO8(ChipCmd, CmdTxEnb | CmdRxEnb);
		WriteMMIO8(ETThReg, ETTh);
			
		// For gigabit rtl8169
		WriteMMIO16(RxMaxSize, static_cast<unsigned short>(hw_rx_pkt_len));

		// Set Rx Config register
		i = r1000_rx_config | (ReadMMIO32(RxConfig) & rtl_chip_info[chipset].RxConfigMask);
		WriteMMIO32(RxConfig, i);
			
		/* Set DMA burst size and Interframe Gap Time */
		WriteMMIO32(TxConfig, (TX_DMA_BURST << TxDMAShift) | (InterFrameGap << TxInterFrameGapShift));

		WriteMMIO16(CPlusCmd, ReadMMIO16(CPlusCmd));
		
		if(mcfg == MCFG_METHOD_2 || mcfg == MCFG_METHOD_3)
		{
			WriteMMIO16(CPlusCmd, (ReadMMIO16(CPlusCmd) | (1 << 14) | (1 << 3)));
			DLog("Set MAC Reg C+CR Offset 0xE0: bit-3 and bit-14\n");
		}
		else
		{
			WriteMMIO16(CPlusCmd, (ReadMMIO16(CPlusCmd) | (1 << 3)));
			DLog("Set MAC Reg C+CR Offset 0xE0: bit-3.\n");
		}
	
		{
			WriteMMIO16(0xE2,0x0000);
		}
		
		//TO-DO: FIX-ME: Fixed?
		
		cur_rx = 0;

		WriteMMIO32(TxDescStartAddr, txdesc_phy_dma_addr);
		WriteMMIO32(TxDescStartAddr + 4, 0x00);
		WriteMMIO32(RxDescStartAddr, rxdesc_phy_dma_addr);
		WriteMMIO32(RxDescStartAddr + 4, 0x00);

		WriteMMIO8(Cfg9346, Cfg9346_Lock);
		IODelay(10);
		
		WriteMMIO32 ( RxMissed, 0 );

		//TO-DO: FIX-ME
		//r1000_set_rx_mode(netdev);

		WriteMMIO16(MultiIntr, ReadMMIO16(MultiIntr) & 0xF000);
		WriteMMIO16(IntrMask, r1000_intr_mask);
	}
	else
	{
		/* Soft reset the chip. */
		WriteMMIO8(ChipCmd, CmdReset);

		/* Check that the chip has finished the reset. */
		for (i = 1000; i > 0; i--)
		{
			if ((ReadMMIO8(ChipCmd) & CmdReset) == 0) break;
			else IODelay(10); //Microseconds
		}	
		
		if (mcfg == MCFG_METHOD_13 )
		{
			pciDev->configWrite16(0x68, 0x00);
			pciDev->configWrite16(0x69, 0x08);
		}
		
		if (mcfg == MCFG_METHOD_5)
		{
			i8 = ReadMMIO8(Config2);
			i8 = i8 & 0x07;
			if (i8 && 0x01)	WriteMMIO32(Off7Ch, 0x0007FFFF);
	
			i = 0x0007FF00;
			WriteMMIO32(Off7Ch, i);

			i16 = pciDev->configRead16(0x04);
			i16 = i16 & 0xEF;
			pciDev->configWrite16(0x04, i16);
		}
		
		WriteMMIO8(Cfg9346, Cfg9346_Unlock);
		WriteMMIO8(ETThReg, ETTh);
		
		// For gigabit rtl8169
		WriteMMIO16(RxMaxSize, static_cast<unsigned short>(hw_rx_pkt_len));

		WriteMMIO16(CPlusCmd, ReadMMIO16(CPlusCmd));
		
		if (mcfg == MCFG_METHOD_2 || mcfg == MCFG_METHOD_3)
		{
			WriteMMIO16(CPlusCmd, (ReadMMIO16(CPlusCmd) | (1 << 14) | (1 << 3)));
			DLog("Set MAC Reg C+CR Offset 0xE0: bit-3 and bit-14\n");
		}
		else
		{
			WriteMMIO16(CPlusCmd, (ReadMMIO16(CPlusCmd) | (1 << 3)));
			DLog("Set MAC Reg C+CR Offset 0xE0: bit-3.\n");
		}
		
		{
			WriteMMIO16(0xE2,0x0000);
		}
		
		//TO-DO: FIX-ME: Fixed?
		cur_rx = 0;

		WriteMMIO32(TxDescStartAddr, txdesc_phy_dma_addr);
		WriteMMIO32(TxDescStartAddr + 4, 0x00);
		WriteMMIO32(RxDescStartAddr, rxdesc_phy_dma_addr);
		WriteMMIO32(RxDescStartAddr + 4, 0x00);
		WriteMMIO8(ChipCmd, CmdTxEnb | CmdRxEnb);
		// Set Rx Config register
		i = r1000_rx_config | (ReadMMIO32(RxConfig) & rtl_chip_info[chipset].RxConfigMask);
		WriteMMIO32(RxConfig, i);

		/* Set DMA burst size and Interframe Gap Time */
		WriteMMIO32(TxConfig, (TX_DMA_BURST << TxDMAShift) | (InterFrameGap << TxInterFrameGapShift));

		WriteMMIO8(Cfg9346, Cfg9346_Lock);
		IODelay(10);
		
		WriteMMIO32 (RxMissed, 0);

		//TO-DO: FIX-ME
		//r1000_set_rx_mode(netdev);

		WriteMMIO16(MultiIntr, ReadMMIO16(MultiIntr) & 0xF000);

		WriteMMIO16(IntrMask, r1000_intr_mask);
	}
	
	//TO-DO: FIX-ME
	//netif_start_queue(netdev);
}

ulong RealtekR1000::ether_crc(int length, unsigned char *data)
{
	int crc = -1;

	while (--length >= 0) 
	{
		unsigned char current_octet = *data++;
		int bit;
		for (bit = 0; bit < 8; bit++, current_octet >>= 1)
			crc = (crc << 1) ^ ((crc < 0) ^ (current_octet & 1) ? ethernet_polynomial : 0);
	}

	return crc;
}


bool RealtekR1000::AllocateDescriptorsMemory()
{
	//Allocating descriptor memory
	IOByteCount len;
	
	sizeof_txdesc_space = NUM_TX_DESC * sizeof(TxDesc) + 256;
	tx_descMd = IOBufferMemoryDescriptor::withOptions(kIOMemoryPhysicallyContiguous,
														sizeof_txdesc_space,
														PAGE_SIZE);