📄 led.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity led is
port( a_in: in std_logic ;
clk_in: in std_logic ;
b_out: out std_logic_vector(3 downto 0)
);
end led ;
--============================================================
architecture behave of led is
signal state: std_logic_vector(1 downto 0) :="00";
signal period: std_logic_vector(23 downto 0) :="000000000000000000000000" ;
signal clk: std_logic :='0';
begin
---------------------=========================================
sec_get:process(clk_in)
begin
if(clk_in'event and clk_in='1') then
if(period="100110001001011010000000") then
clk<=not clk;
period<="000000000000000000000000";
else
period<=period+1;
end if;
end if;
end process ;
--------------------==========================================
state_change:process(a_in)
begin
if(a_in'event and a_in='1') then
state<=state+1;
end if;
end process;
---------------------==========================================
light:process(clk)
begin
case state is
when "00" => if(clk='0') then
b_out <= "0000";
else
b_out <= "1111";
end if;
when "01" => if(clk='0') then
b_out <= "0011";
else
b_out <= "1100";
end if;
when "10" => if(clk='0') then
b_out <= "0101";
else
b_out <= "1010";
end if;
when "11" => if(clk='0') then
b_out <= "1001";
else
b_out <= "0110";
end if;
when others => b_out <= "0000";
end case;
end process;
end behave;
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