ems_pci.c

can4linux-3.5.3.gz can4 linux

     * at address 0x400 the first controller area 
     * at address 0x600 the second controller area 
     * registers are read as 32bit
     *
     * at adress 0 we can verify the card
     * 0x55 0xaa 0x01 0xcb
*/
    {
	void __iomem *sigptr; /* ptr to EMS signature  */
	unsigned long signature = 0;
	sigptr = (void __iomem *)ioremap(PCI_BASE_ADDRESS1(pdev), 256);
	signature =
		  (readb(sigptr)      << 24)
		+ (readb(sigptr +  4) << 16)
		+ (readb(sigptr +  8) <<  8)
		+  readb(sigptr + 12);
	/* printk("        signature  %lx\n", signature); */
	if( 0x55aa01cb != signature) {
	    printk(" wrong signature -- no EMS CPC-PCI board\n");
	    return -ENODEV;
	}
    }
    /* we are now sure to have the right board,
       reset the CAN controller(s) */
    reset_CPC_PCI(PCI_BASE_ADDRESS1(pdev) + 0x400);
    reset_CPC_PCI(PCI_BASE_ADDRESS1(pdev) + 0x600);

    /* enable interrupts Int_0 */
    /* write to PITAs ICR register */
    writel(PITA2_ICR_INT0_EN,
    (void __iomem *)Can_pitapci_control[i] + PITA2_ICR);

    err("int i ist %d", i);
    /* look for a CAN controller at 0x400 */
    if(controller_available(PCI_BASE_ADDRESS1(pdev) + 0x400, 4)) {
	printk(" CAN: %d. at pos 1\n", i);
	if(i > MAX_CHANNELS) {
	    printk("CAN: only %d devices supported\n", MAX_CHANNELS);
	    return i; /* the devices scan loop */
	}
	Base[i]
	= (unsigned long)ioremap(PCI_BASE_ADDRESS1(pdev) + 0x400, 32*4);
	IOModel[i] = 'm';
	IRQ[i] = pdev->irq;
	i++;
    } else {
	/* printk(" CAN: NO at pos 1\n"); */
	;
    }

    err("int i ist %d", i);
    /* look for a second CAN controller at 0x400 */
    if(controller_available(PCI_BASE_ADDRESS1(pdev) + 0x600, 4)) {
	printk(" CAN: %d. at pos 2\n", i);
	if(i > MAX_CHANNELS) {
	    printk("CAN: only %d devices supported\n", MAX_CHANNELS);
	    return i; /* the devices scan loop */
	}
	/* share the board control register with prev ch */
	Can_pitapci_control[i] = 
	    Can_pitapci_control[i - 1];
	Base[i]
	= (unsigned long)ioremap(PCI_BASE_ADDRESS1(pdev) + 0x600, 32*4);
	IOModel[i] = 'm';
	IRQ[i] = pdev->irq;
	i++;
    } else {
	/* printk(" CAN: NO at pos 2\n"); */
	;
    }

    err("int i ist %d", i);
    DBGout();
    return i;
}

int new_pcimod_scan(void)
{
struct	pci_dev *pdev = NULL;
int	candev = 0;			/* number of found devices */
int	minor = -1;			/* to make DBGin() happy */

    DBGin();
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
    /* Testing the PCI presence is no longer neccessary
     * On a non  PCI kernel, insmod will just complain
     */
    if (pci_present ()) {
#endif

    for_each_pci_dev(pdev) {
	if(pdev->vendor == PCI_VENDOR_ID_PLX
	&& pdev->device == PCI_DEVICE_ID_PLX_9030) {
	    err("found new EMS pci board %d", candev);
	    printk("Subsystem Vendor 0x%0x\n", pdev->subsystem_vendor);
	    printk("Subsystem Device 0x%0x\n", pdev->subsystem_device);
	    /* reading delivers 0x10b5, 0x4000 */
	    if (pci_enable_device(pdev)) {
		    continue;
	    } else {
		candev += register_new_cpcpci(pdev, candev);
	    }
	}
	if(pdev->vendor == PCI_VENDOR_CAN_EMS
	&& pdev->device == PCI_DEVICE_CAN) {
	    err("found old EMS pci board %d", candev);
	    if (pci_enable_device(pdev)) {
		    continue;
	    } else {
		candev += register_old_cpcpci(pdev, candev);
		;
	    }
	}
    }
    if(candev == 0) {
	err("No CAN device found");
	return -ENODEV;
    } else {
    	err("found %d CAN controllers", candev);
    }

#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
    } else { 
        err("No PCI bios present");
        return -ENODEV;
    }
#endif
    DBGout();
    return 0;
}


/* Should be replaced by  new_pcimod_scan() soon
 * to be able to handle both kinds of CPC-PCI
 * hopefully for both boards with the same driver
 * and if possible for the Kvaser PCI as well
 */
/* int old_pcimod_scan(void) */
int pcimod_scan(void)

{
struct	pci_dev *pdev = NULL;
int	candev = 0;				/* number of found devices */
unsigned long ptr;				/* ptr to PITA control */

#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
    /* Testing the PCI presence is no longer neccessary
     * On a non  PCI kernel, insmod will just complain
     */
    if (pci_present ()) {
#endif
	    while((pdev =
	    	pci_get_device (PCI_VENDOR_CAN_EMS, PCI_DEVICE_CAN, pdev))) {

#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
	    printk("  found CPC-PCI: %s\n", pdev->name);
#else
	    printk("  found CPC-PCI: %s\n", pci_pretty_name(pdev));
	    printk("               : %s\n", pci_name(pdev));
#endif
	    if (pci_enable_device(pdev)) {
		continue;
	    }
	    /* printk("        using IRQ %d\n", pdev->irq); */

	    ptr = (unsigned long)ioremap(PCI_BASE_ADDRESS0(pdev), 256);
	    /* enable memory access */
	    /* printk("write to pita\n"); */
	    writel(PITA2_MISC_CONFIG, (void __iomem *)ptr + PITA2_MISC);
	    Can_pitapci_control[candev] = ptr;

	    /* printk("        pita ptr %lx\n", ptr); */
	    /* printk("---------------\n"); */
	    /* dump_CAN(PCI_BASE_ADDRESS1(pdev)+0x400, 4); */
	    /* printk("---------------\n"); */
	    /* dump_CAN(PCI_BASE_ADDRESS1(pdev)+0x600, 4); */

	    /* PCI_BASE_ADDRESS1:
	     * at address 0 are some EMS control registers
	     * at address 0x400 the first controller area 
	     * at address 0x600 the second controller area 
	     * registers are read as 32bit
	     *
	     * at adress 0 we can verify the card
	     * 0x55 0xaa 0x01 0xcb
     */
	    {
		void __iomem *sigptr; /* ptr to EMS signature  */
		unsigned long signature = 0;
	        sigptr = (void __iomem *)ioremap(PCI_BASE_ADDRESS1(pdev), 256);
	        signature =
	        	  (readb(sigptr)      << 24)
	        	+ (readb(sigptr +  4) << 16)
	        	+ (readb(sigptr +  8) <<  8)
	        	+  readb(sigptr + 12);
	    	/* printk("        signature  %lx\n", signature); */
	    	if( 0x55aa01cb != signature) {
	    	    printk(" wrong signature -- no EMS CPC-PCI board\n");
		    return -ENODEV;
	    	}
	    }
	    /* we are now sure to have the right board,
	       reset the CAN controller(s) */
	    reset_CPC_PCI(PCI_BASE_ADDRESS1(pdev) + 0x400);
	    reset_CPC_PCI(PCI_BASE_ADDRESS1(pdev) + 0x600);

	    /* enable interrupts Int_0 */
	    /* write to PITAs ICR register */
	    writel(PITA2_ICR_INT0_EN,
	    (void __iomem *)Can_pitapci_control[candev] + PITA2_ICR);

	    /* look for a CAN controller at 0x400 */
	    if(controller_available(PCI_BASE_ADDRESS1(pdev) + 0x400, 4)) {
		printk(" CAN: %d. at pos 1\n", candev + 1);
		if(candev > MAX_CHANNELS) {
		    printk("CAN: only %d devices supported\n", MAX_CHANNELS);
		    break; /* the devices scan loop */
		}
		Base[candev]
		= (unsigned long)ioremap(PCI_BASE_ADDRESS1(pdev) + 0x400, 32*4);
		IOModel[candev] = 'm';
		IRQ[candev] = pdev->irq;
		candev++;
	    } else {
		/* printk(" CAN: NO at pos 1\n"); */
		;
	    }
	    /* look for a second CAN controller at 0x400 */
	    if(controller_available(PCI_BASE_ADDRESS1(pdev) + 0x600, 4)) {
		printk(" CAN: %d. at pos 2\n", candev + 1);
		if(candev > MAX_CHANNELS) {
		    printk("CAN: only %d devices supported\n", MAX_CHANNELS);
		    break; /* the devices scan loop */
		}
		/* share the board control register with prev ch */
		Can_pitapci_control[candev] = 
		    Can_pitapci_control[candev - 1];
		Base[candev]
		= (unsigned long)ioremap(PCI_BASE_ADDRESS1(pdev) + 0x600, 32*4);
		IOModel[candev] = 'm';
		IRQ[candev] = pdev->irq;
		candev++;
	    } else {
		/* printk(" CAN: NO at pos 2\n"); */
		;
	    }
	}
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
    } else {
        printk("CAN: No PCI bios present\n");
        return -ENODEV;
    }
#endif
    return 0;
}


void board_clear_interrupts(int minor)
{

/* old  Siemens PITA */
    /* Interrupt_0_Enable (bit 17) + Int_0_Reset (bit 1) */
    /*  
     Uttenthaler:
      nur 
        writel(0x00020002, Can_pitapci_control[minor] + 0x0);
      als letzte Anweisung in der ISR
     Schoett:
      bei Eintritt
        writel(0x00000000, Can_pitapci_control[minor] + 0x0);
      am ende
        writel(0x00020002, Can_pitapci_control[minor] + 0x0);
    */
    writel(0x00020002, (void __iomem *)Can_pitapci_control[minor] + 0x0);
    writel(0x00020000, (void __iomem *)Can_pitapci_control[minor] + 0x0);

/* new */

    writel(PLX9030_ICR_CLEAR_IRQ0 | PLX9030_ICR_ENABLE_IRQ0,
          (void __iomem *)Can_pitapci_control[minor] + PLX9030_ICR);

}
# endif 	/* defined(CPC_PCI) */

#endif