fentclk.twr

FPGA高速完成AD采集回来的数据进行高速读写FLASH存储

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Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -ise d:\2222\2222.ise -intstyle ise -e 3 -l 3 -s 6
-xml fentclk fentclk.ncd -o fentclk.twr fentclk.pcf


Design file:              fentclk.ncd
Physical constraint file: fentclk.pcf
Device,speed:             xc2s100e,-6 (PRODUCTION 1.18 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock fosc60m to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
refclk      |    6.436(R)|fosc60m_BUFGP     |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock fosc60m
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
fosc60m        |    2.963|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Mon Sep 29 16:14:27 2008
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Peak Memory Usage: 69 MB