dd.vhd

来自「FPGA高速完成AD采集回来的数据进行高速读写FLASH存储」· VHDL 代码 · 共 29 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY grst IS
	PORT(
			fosc60m : IN STD_LOGIC;
			grst : OUT STD_LOGIC
			);
END grst;

ARCHITECTURE Behavioral OF grst IS
BEGIN

	PROCESS(fosc60m)
		VARIABLE cnt : INTEGER RANGE 0 TO 6000000;
	BEGIN
		IF fosc60m'event AND fosc60m = '1' THEN			
			IF cnt < 5999999 THEN
			     cnt := cnt + 1;
				grst <= '0';
			ELSE
				grst <= '1';
			END IF;
		END IF;
	END PROCESS;

END Behavioral;