clk60.twr

来自「FPGA高速完成AD采集回来的数据进行高速读写FLASH存储」· TWR 代码 · 共 42 行

--------------------------------------------------------------------------------
Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -ise d:\2222\2222.ise -intstyle ise -e 3 -l 3 -s 6
-xml clk60 clk60.ncd -o clk60.twr clk60.pcf


Design file:              clk60.ncd
Physical constraint file: clk60.pcf
Device,speed:             xc2s100e,-6 (PRODUCTION 1.18 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
fosc           |fosc60m        |    6.371|
---------------+---------------+---------+

Analysis completed Tue Sep 30 08:52:19 2008
--------------------------------------------------------------------------------



Peak Memory Usage: 69 MB