data_unite.vhd

FPGA高速完成AD采集回来的数据进行高速读写FLASH存储

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity data_unite is
	port(
		datain1:in std_logic_vector(1 downto 0);
		datain2:in std_logic_vector(1 downto 0);
		datain3:in std_logic_vector(1 downto 0);
		datain4:in std_logic_vector(1 downto 0);
		datain5:in std_logic_vector(1 downto 0);
		datain6:in std_logic_vector(1 downto 0);
		dataout:out std_logic_vector(11 downto 0)
	);
end data_unite;

architecture Behavioral of data_unite is

begin
	dataout<=datain6 & datain5 & datain4 & datain3 & datain2 & datain1; 

end Behavioral;