rece.twr

FPGA高速完成AD采集回来的数据进行高速读写FLASH存储

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Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -ise d:\2222\2222.ise -intstyle ise -e 3 -l 3 -s 6
-xml rece rece.ncd -o rece.twr rece.pcf


Design file:              rece.ncd
Physical constraint file: rece.pcf
Device,speed:             xc2s100e,-6 (PRODUCTION 1.18 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock rclk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
lock        |    4.283(F)|    3.086(F)|XLXN_3            |   0.000|
rout<0>     |   -2.022(F)|    3.426(F)|XLXN_3            |   0.000|
rout<10>    |   -2.334(F)|    3.426(F)|XLXN_3            |   0.000|
rout<11>    |   -2.334(F)|    3.426(F)|XLXN_3            |   0.000|
rout<12>    |   -2.334(F)|    3.426(F)|XLXN_3            |   0.000|
rout<13>    |   -2.192(F)|    3.482(F)|XLXN_3            |   0.000|
rout<14>    |   -2.081(F)|    3.482(F)|XLXN_3            |   0.000|
rout<15>    |   -2.142(F)|    3.472(F)|XLXN_3            |   0.000|
rout<16>    |   -2.076(F)|    3.425(F)|XLXN_3            |   0.000|
rout<17>    |   -2.375(F)|    3.467(F)|XLXN_3            |   0.000|
rout<1>     |   -2.170(F)|    3.481(F)|XLXN_3            |   0.000|
rout<2>     |   -2.389(F)|    3.481(F)|XLXN_3            |   0.000|
rout<3>     |   -2.333(F)|    3.425(F)|XLXN_3            |   0.000|
rout<4>     |   -2.301(F)|    3.425(F)|XLXN_3            |   0.000|
rout<5>     |   -2.088(F)|    3.425(F)|XLXN_3            |   0.000|
rout<6>     |   -2.237(F)|    3.425(F)|XLXN_3            |   0.000|
rout<7>     |   -2.153(F)|    3.425(F)|XLXN_3            |   0.000|
rout<8>     |   -2.389(F)|    3.481(F)|XLXN_3            |   0.000|
rout<9>     |   -2.389(F)|    3.481(F)|XLXN_3            |   0.000|
------------+------------+------------+------------------+--------+

Clock rclk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
dout<0>     |   14.929(F)|XLXN_3            |   0.000|
dout<10>    |   13.266(F)|XLXN_3            |   0.000|
dout<11>    |   13.187(F)|XLXN_3            |   0.000|
dout<12>    |   12.720(F)|XLXN_3            |   0.000|
dout<13>    |   12.946(F)|XLXN_3            |   0.000|
dout<14>    |   12.704(F)|XLXN_3            |   0.000|
dout<15>    |   12.661(F)|XLXN_3            |   0.000|
dout<16>    |   13.188(F)|XLXN_3            |   0.000|
dout<17>    |   11.951(F)|XLXN_3            |   0.000|
dout<1>     |   15.510(F)|XLXN_3            |   0.000|
dout<2>     |   14.725(F)|XLXN_3            |   0.000|
dout<3>     |   15.450(F)|XLXN_3            |   0.000|
dout<4>     |   14.650(F)|XLXN_3            |   0.000|
dout<5>     |   14.946(F)|XLXN_3            |   0.000|
dout<6>     |   14.876(F)|XLXN_3            |   0.000|
dout<7>     |   14.560(F)|XLXN_3            |   0.000|
dout<8>     |   13.564(F)|XLXN_3            |   0.000|
dout<9>     |   14.001(F)|XLXN_3            |   0.000|
led1        |    9.865(F)|XLXN_3            |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock rclk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
rclk           |         |         |         |    8.715|
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
fosc           |refclk         |    7.460|
---------------+---------------+---------+

Analysis completed Tue Oct 14 16:54:26 2008
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Peak Memory Usage: 69 MB