fifo12bit_2k.syr

FPGA高速完成AD采集回来的数据进行高速读写FLASH存储

    Set user-defined property "INIT_08 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <XLXI_8> in unit <fifo12bit_2k>.
    Set user-defined property "INIT_09 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <XLXI_8> in unit <fifo12bit_2k>.
    Set user-defined property "INIT_0A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <XLXI_8> in unit <fifo12bit_2k>.
    Set user-defined property "INIT_0B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <XLXI_8> in unit <fifo12bit_2k>.
    Set user-defined property "INIT_0C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <XLXI_8> in unit <fifo12bit_2k>.
    Set user-defined property "INIT_0D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <XLXI_8> in unit <fifo12bit_2k>.
    Set user-defined property "INIT_0E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <XLXI_8> in unit <fifo12bit_2k>.
    Set user-defined property "INIT_0F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <XLXI_8> in unit <fifo12bit_2k>.
Entity <fifo12bit_2k> analyzed. Unit <fifo12bit_2k> generated.

Analyzing Entity <data_part> (Architecture <behavioral>).
Entity <data_part> analyzed. Unit <data_part> generated.

Analyzing Entity <data_unite> (Architecture <behavioral>).
Entity <data_unite> analyzed. Unit <data_unite> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <data_unite>.
    Related source file is "D:/2222/data_unite.vhd".
Unit <data_unite> synthesized.


Synthesizing Unit <data_part>.
    Related source file is "D:/2222/data_part.vhd".
Unit <data_part> synthesized.


Synthesizing Unit <fifo12bit_2k>.
    Related source file is "D:/2222/fifo12bit_2k.vhf".
Unit <fifo12bit_2k> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <fifo12bit_2k> ...
Loading device for application Rf_Device from file '2s100e.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block fifo12bit_2k, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : fifo12bit_2k.ngr
Top Level Output File Name         : fifo12bit_2k
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 48

Cell Usage :
# BELS                             : 5
#      GND                         : 3
#      VCC                         : 2
# RAMS                             : 6
#      RAMB4_S2_S2                 : 6
# Clock Buffers                    : 2
#      BUFGP                       : 2
# IO Buffers                       : 46
#      IBUF                        : 34
#      OBUF                        : 12
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100etq144-6 

 Number of bonded IOBs:                 48  out of    102    47%  
 Number of BRAMs:                        6  out of     10    60%  
 Number of GCLKs:                        2  out of      4    50%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
fifowr                             | BUFGP                  | 6     |
fiford                             | BUFGP                  | 6     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: 2.647ns
   Maximum output required time after clock: 8.742ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'fifowr'
  Total number of paths / destination ports: 78 / 78
-------------------------------------------------------------------------
Offset:              2.647ns (Levels of Logic = 1)
  Source:            adda<10> (PAD)
  Destination:       XLXI_3 (RAM)
  Destination Clock: fifowr rising

  Data Path: adda<10> to XLXI_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             6   0.797   1.850  adda_10_IBUF (adda_10_IBUF)
     RAMB4_S2_S2:ADDRA10        0.000          XLXI_8
    ----------------------------------------
    Total                      2.647ns (0.797ns logic, 1.850ns route)
                                       (30.1% logic, 69.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'fiford'
  Total number of paths / destination ports: 78 / 78
-------------------------------------------------------------------------
Offset:              2.647ns (Levels of Logic = 1)
  Source:            addb<10> (PAD)
  Destination:       XLXI_3 (RAM)
  Destination Clock: fiford rising

  Data Path: addb<10> to XLXI_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             6   0.797   1.850  addb_10_IBUF (addb_10_IBUF)
     RAMB4_S2_S2:ADDRB10        0.000          XLXI_8
    ----------------------------------------
    Total                      2.647ns (0.797ns logic, 1.850ns route)
                                       (30.1% logic, 69.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'fiford'
  Total number of paths / destination ports: 12 / 12
-------------------------------------------------------------------------
Offset:              8.742ns (Levels of Logic = 1)
  Source:            XLXI_8 (RAM)
  Destination:       dataout<11> (PAD)
  Source Clock:      fiford rising

  Data Path: XLXI_8 to dataout<11>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     RAMB4_S2_S2:CLKB->DOB1    1   3.220   0.920  XLXI_8 (XLXN_49<1>)
     OBUF:I->O                 4.602          dataout_11_OBUF (dataout<11>)
    ----------------------------------------
    Total                      8.742ns (7.822ns logic, 0.920ns route)
                                       (89.5% logic, 10.5% route)

=========================================================================
CPU : 11.58 / 12.06 s | Elapsed : 12.00 / 12.00 s
 
--> 

Total memory usage is 89660 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)