clk60.vhf

FPGA高速完成AD采集回来的数据进行高速读写FLASH存储

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-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
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--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 7.1i
--  \   \         Application : sch2vhdl
--  /   /         Filename : clk60.vhf
-- /___/   /\     Timestamp : 09/29/2008 22:39:23
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: D:/Xilinx/bin/nt/sch2vhdl.exe -intstyle ise -family spartan2e -flat -suppress -w clk60.sch clk60.vhf
--Design Name: clk60
--Device: spartan2e
--Purpose:
--    This vhdl netlist is translated from an ECS schematic. It can be 
--    synthesis and simulted, but it should not be modified. 
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity clk60 is
   port ( fosc    : in    std_logic; 
          fosc60m : out   std_logic);
end clk60;

architecture BEHAVIORAL of clk60 is
   attribute CLKDV_DIVIDE          : string ;
   attribute DUTY_CYCLE_CORRECTION : string ;
   attribute BOX_TYPE              : string ;
   signal XLXN_1        : std_logic;
   signal XLXN_2        : std_logic;
   signal XLXN_4        : std_logic;
   signal fosc60m_DUMMY : std_logic;
   component CLKDLL
      -- synopsys translate_off
      generic( CLKDV_DIVIDE : real :=  2.000000);
      -- synopsys translate_on
      port ( CLKFB  : in    std_logic; 
             CLKIN  : in    std_logic; 
             RST    : in    std_logic; 
             CLK0   : out   std_logic; 
             CLK180 : out   std_logic; 
             CLK270 : out   std_logic; 
             CLK2X  : out   std_logic; 
             CLK90  : out   std_logic; 
             CLKDV  : out   std_logic; 
             LOCKED : out   std_logic);
   end component;
   attribute CLKDV_DIVIDE of CLKDLL : component is "2.000000";
   attribute DUTY_CYCLE_CORRECTION of CLKDLL : component is "TRUE";
   attribute BOX_TYPE of CLKDLL : component is "BLACK_BOX";
   
   component IBUFG
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   attribute BOX_TYPE of IBUFG : component is "BLACK_BOX";
   
   component BUFG
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   attribute BOX_TYPE of BUFG : component is "BLACK_BOX";
   
   component GND
      port ( G : out   std_logic);
   end component;
   attribute BOX_TYPE of GND : component is "BLACK_BOX";
   
begin
   fosc60m <= fosc60m_DUMMY;
   XLXI_1 : CLKDLL
      port map (CLKFB=>fosc60m_DUMMY,
                CLKIN=>XLXN_2,
                RST=>XLXN_4,
                CLKDV=>open,
                CLK0=>XLXN_1,
                CLK2X=>open,
                CLK90=>open,
                CLK180=>open,
                CLK270=>open,
                LOCKED=>open);
   
   XLXI_2 : IBUFG
      port map (I=>fosc,
                O=>XLXN_2);
   
   XLXI_3 : BUFG
      port map (I=>XLXN_1,
                O=>fosc60m_DUMMY);
   
   XLXI_4 : GND
      port map (G=>XLXN_4);
   
end BEHAVIORAL;