fifo12bit_2k.par

FPGA高速完成AD采集回来的数据进行高速读写FLASH存储

Release 7.1i par H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

B5A6955F24534CE::  Mon Oct 13 11:06:09 2008

par -w -intstyle ise -ol std -t 1 fifo12bit_2k_map.ncd fifo12bit_2k.ncd
fifo12bit_2k.pcf 


Constraints file: fifo12bit_2k.pcf.
Loading device for application Rf_Device from file '2s100e.nph' in environment
D:/Xilinx.
   "fifo12bit_2k" is an NCD, version 3.1, device xc2s100e, package tq144, speed
-6

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 85.000
Celsius)
Initializing voltage to 1.700 Volts. (default - Range: 1.700 to 1.900 Volts)


Device speed data version:  "PRODUCTION 1.18 2005-01-22".


Device Utilization Summary:

   Number of BLOCKRAMs                 6 out of 10     60%
   Number of GCLKs                     2 out of 4      50%
   Number of External GCLKIOBs         2 out of 4      50%
      Number of LOCed GCLKIOBs         0 out of 2       0%

   Number of External IOBs            46 out of 98     46%
      Number of LOCed IOBs             0 out of 46      0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98975f) REAL time: 0 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.23
Phase 3.23 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 0 secs 

Phase 6.8
..........................
Phase 6.8 (Checksum:9df197) REAL time: 0 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 0 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 0 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 0 secs 

Writing design to file fifo12bit_2k.ncd


Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 

Starting Router

Phase 1: 182 unrouted;       REAL time: 0 secs 

Phase 2: 170 unrouted;       REAL time: 0 secs 

Phase 3: 60 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|        fiford_BUFGP |      GCLKBUF1| No   |    6 |  0.024     |  0.285      |
+---------------------+--------------+------+------+------------+-------------+
|        fifowr_BUFGP |      GCLKBUF0| No   |    6 |  0.024     |  0.285      |
+---------------------+--------------+------+------+------------+-------------+

INFO:Par:340 - 
   The Delay report will not be generated when running non-timing driven PAR
   with effort level Standard or Medium. If a delay report is required please do
   one of the following:  1) use effort level High, 2) use the following
   environment variable "XIL_PAR_GENERATE_DLY_REPORT", 3) create Timing
   constraints for the design.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 1 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  67 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file fifo12bit_2k.ncd



PAR done!