rece18.twr

FPGA高速完成AD采集回来的数据进行高速读写FLASH存储

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Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -ise d:\2222\2222.ise -intstyle ise -e 3 -l 3 -s 6
-xml rece18 rece18.ncd -o rece18.twr rece18.pcf


Design file:              rece18.ncd
Physical constraint file: rece18.pcf
Device,speed:             xc2s100e,-6 (PRODUCTION 1.18 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock rclk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
lock        |    4.325(F)|   -0.543(F)|rclk_BUFGP        |   0.000|
rout<0>     |    1.800(F)|    0.000(F)|rclk_BUFGP        |   0.000|
rout<10>    |    1.800(F)|    0.000(F)|rclk_BUFGP        |   0.000|
rout<11>    |    1.800(F)|    0.000(F)|rclk_BUFGP        |   0.000|
rout<12>    |    1.800(F)|    0.000(F)|rclk_BUFGP        |   0.000|
rout<13>    |    1.800(F)|    0.000(F)|rclk_BUFGP        |   0.000|
rout<14>    |    1.800(F)|    0.000(F)|rclk_BUFGP        |   0.000|
rout<15>    |    1.800(F)|    0.000(F)|rclk_BUFGP        |   0.000|
rout<16>    |    1.800(F)|    0.000(F)|rclk_BUFGP        |   0.000|
rout<17>    |    1.800(F)|    0.000(F)|rclk_BUFGP        |   0.000|
rout<1>     |    1.800(F)|    0.000(F)|rclk_BUFGP        |   0.000|
rout<2>     |    1.800(F)|    0.000(F)|rclk_BUFGP        |   0.000|
rout<3>     |    1.800(F)|    0.000(F)|rclk_BUFGP        |   0.000|
rout<4>     |    1.800(F)|    0.000(F)|rclk_BUFGP        |   0.000|
rout<5>     |    1.800(F)|    0.000(F)|rclk_BUFGP        |   0.000|
rout<6>     |    1.800(F)|    0.000(F)|rclk_BUFGP        |   0.000|
rout<7>     |    1.800(F)|    0.000(F)|rclk_BUFGP        |   0.000|
rout<8>     |    1.800(F)|    0.000(F)|rclk_BUFGP        |   0.000|
rout<9>     |    1.800(F)|    0.000(F)|rclk_BUFGP        |   0.000|
------------+------------+------------+------------------+--------+

Clock rclk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
dout<0>     |    9.720(F)|rclk_BUFGP        |   0.000|
dout<10>    |    9.429(F)|rclk_BUFGP        |   0.000|
dout<11>    |   10.401(F)|rclk_BUFGP        |   0.000|
dout<12>    |    8.299(F)|rclk_BUFGP        |   0.000|
dout<13>    |    8.344(F)|rclk_BUFGP        |   0.000|
dout<14>    |    7.632(F)|rclk_BUFGP        |   0.000|
dout<15>    |    8.283(F)|rclk_BUFGP        |   0.000|
dout<16>    |    8.283(F)|rclk_BUFGP        |   0.000|
dout<17>    |    8.133(F)|rclk_BUFGP        |   0.000|
dout<1>     |    7.696(F)|rclk_BUFGP        |   0.000|
dout<2>     |    7.658(F)|rclk_BUFGP        |   0.000|
dout<3>     |    8.871(F)|rclk_BUFGP        |   0.000|
dout<4>     |    9.140(F)|rclk_BUFGP        |   0.000|
dout<5>     |    8.702(F)|rclk_BUFGP        |   0.000|
dout<6>     |    8.939(F)|rclk_BUFGP        |   0.000|
dout<7>     |    9.316(F)|rclk_BUFGP        |   0.000|
dout<8>     |   10.124(F)|rclk_BUFGP        |   0.000|
dout<9>     |   10.059(F)|rclk_BUFGP        |   0.000|
led1        |    6.430(F)|rclk_BUFGP        |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock rclk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
rclk           |         |         |         |    8.142|
---------------+---------+---------+---------+---------+

Analysis completed Mon Oct 13 22:15:41 2008
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Peak Memory Usage: 69 MB